CA1244554A - Pageable branch history table - Google Patents

Pageable branch history table

Info

Publication number
CA1244554A
CA1244554A CA000502802A CA502802A CA1244554A CA 1244554 A CA1244554 A CA 1244554A CA 000502802 A CA000502802 A CA 000502802A CA 502802 A CA502802 A CA 502802A CA 1244554 A CA1244554 A CA 1244554A
Authority
CA
Canada
Prior art keywords
segment
branch
entries
entry
active area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000502802A
Other languages
English (en)
French (fr)
Inventor
James H. Pomerene
Thomas R. Puzak
Rudolph N. Rechtschaffen
Frank J. Sparacio
Philip L. Rosenfeld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1244554A publication Critical patent/CA1244554A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA000502802A 1985-04-29 1986-02-26 Pageable branch history table Expired CA1244554A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/728,424 US4679141A (en) 1985-04-29 1985-04-29 Pageable branch history table
US728,424 1985-04-29

Publications (1)

Publication Number Publication Date
CA1244554A true CA1244554A (en) 1988-11-08

Family

ID=24926799

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000502802A Expired CA1244554A (en) 1985-04-29 1986-02-26 Pageable branch history table

Country Status (5)

Country Link
US (1) US4679141A (esLanguage)
EP (1) EP0199947B1 (esLanguage)
JP (1) JPS61250738A (esLanguage)
CA (1) CA1244554A (esLanguage)
DE (1) DE3682700D1 (esLanguage)

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US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
WO1991013402A1 (en) * 1990-02-26 1991-09-05 Nexgen Microsystems Two-level branch prediction cache
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KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
WO1994027210A1 (en) * 1993-05-14 1994-11-24 Intel Corporation Speculative history mechanism in a branch target buffer
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JP2801135B2 (ja) * 1993-11-26 1998-09-21 富士通株式会社 パイプラインプロセッサの命令読み出し方法及び命令読み出し装置
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
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US5634119A (en) * 1995-01-06 1997-05-27 International Business Machines Corporation Computer processing unit employing a separate millicode branch history table
JP3494736B2 (ja) * 1995-02-27 2004-02-09 株式会社ルネサステクノロジ 分岐先バッファを用いた分岐予測システム
US6185674B1 (en) 1995-04-05 2001-02-06 International Business Machines Corporation Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor
US5699536A (en) * 1995-04-13 1997-12-16 International Business Machines Corporation Computer processing system employing dynamic instruction formatting
US5649178A (en) * 1995-06-07 1997-07-15 International Business Machines, Corporation Apparatus and method for storing and initializing branch prediction with selective information transfer
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5742805A (en) * 1996-02-15 1998-04-21 Fujitsu Ltd. Method and apparatus for a single history register based branch predictor in a superscalar microprocessor
DE69715280T2 (de) * 1996-03-25 2003-08-07 Sun Microsystems, Inc. Verfahren zur Sprungvorhersage in einem mehrstufigen Cachespeichersystem
US5794024A (en) * 1996-03-25 1998-08-11 International Business Machines Corporation Method and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch misprediction
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
US5875325A (en) * 1996-09-19 1999-02-23 International Business Machines Corporation Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history
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US7493480B2 (en) * 2002-07-18 2009-02-17 International Business Machines Corporation Method and apparatus for prefetching branch history information
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US7461209B2 (en) 2005-12-06 2008-12-02 International Business Machines Corporation Transient cache storage with discard function for disposable data
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US8131982B2 (en) * 2008-06-13 2012-03-06 International Business Machines Corporation Branch prediction instructions having mask values involving unloading and loading branch history data
US10338923B2 (en) * 2009-05-05 2019-07-02 International Business Machines Corporation Branch prediction path wrong guess instruction
US8521999B2 (en) * 2010-03-11 2013-08-27 International Business Machines Corporation Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
US9032191B2 (en) 2012-01-23 2015-05-12 International Business Machines Corporation Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels
US8935694B2 (en) 2012-01-23 2015-01-13 International Business Machines Corporation System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions
US9146739B2 (en) * 2012-06-14 2015-09-29 International Business Machines Corporation Branch prediction preloading
US20140025894A1 (en) * 2012-07-18 2014-01-23 Electronics And Telecommunications Research Institute Processor using branch instruction execution cache and method of operating the same
US9507597B2 (en) 2013-06-10 2016-11-29 Via Alliance Semiconductor Co., Ltd. Selective accumulation and use of predicting unit history
US9891918B2 (en) 2014-01-27 2018-02-13 Via Alliance Semiconductor Co., Ltd. Fractional use of prediction history storage for operating system routines
US20150268961A1 (en) * 2014-03-21 2015-09-24 Samsung Electronics Co., Ltd. Decoupling l2 btb from l2 cache to accelerate search for miss after miss
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Also Published As

Publication number Publication date
DE3682700D1 (de) 1992-01-16
EP0199947B1 (en) 1991-12-04
JPS61250738A (ja) 1986-11-07
US4679141A (en) 1987-07-07
EP0199947A3 (en) 1988-12-21
EP0199947A2 (en) 1986-11-05
JPH0318211B2 (esLanguage) 1991-03-12

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