CA1225749A - Data processing system with a plurality of processors accessing a common bus to interleaved storage - Google Patents

Data processing system with a plurality of processors accessing a common bus to interleaved storage

Info

Publication number
CA1225749A
CA1225749A CA000481595A CA481595A CA1225749A CA 1225749 A CA1225749 A CA 1225749A CA 000481595 A CA000481595 A CA 000481595A CA 481595 A CA481595 A CA 481595A CA 1225749 A CA1225749 A CA 1225749A
Authority
CA
Canada
Prior art keywords
bus
address
storage
transfer
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000481595A
Other languages
English (en)
French (fr)
Inventor
Charles G. Wright
Donald E. Waldecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1225749A publication Critical patent/CA1225749A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
CA000481595A 1984-07-31 1985-05-15 Data processing system with a plurality of processors accessing a common bus to interleaved storage Expired CA1225749A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US636,188 1984-07-31
US06/636,188 US4669056A (en) 1984-07-31 1984-07-31 Data processing system with a plurality of processors accessing a common bus to interleaved storage

Publications (1)

Publication Number Publication Date
CA1225749A true CA1225749A (en) 1987-08-18

Family

ID=24550825

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000481595A Expired CA1225749A (en) 1984-07-31 1985-05-15 Data processing system with a plurality of processors accessing a common bus to interleaved storage

Country Status (5)

Country Link
US (1) US4669056A (OSRAM)
EP (1) EP0170021B1 (OSRAM)
JP (1) JPS6142049A (OSRAM)
CA (1) CA1225749A (OSRAM)
DE (1) DE3584402D1 (OSRAM)

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US4797815A (en) * 1985-11-22 1989-01-10 Paradyne Corporation Interleaved synchronous bus access protocol for a shared memory multi-processor system
DE3785958D1 (de) * 1986-04-02 1993-07-01 Siemens Ag Verfahren zum ansteuern eines gemeinsamen speichers eines aus einzelnen mikroprozessorsystemen bestehenden mehrprozessorsystems.
JPS6356754A (ja) * 1986-08-28 1988-03-11 Toshiba Corp 入出力チヤネル
EP0261751A3 (en) * 1986-09-25 1990-07-18 Tektronix, Inc. Concurrent memory access system
US5123100A (en) * 1989-01-13 1992-06-16 Nec Corporation Timing control method in a common bus system having delay and phase correcting circuits for transferring data in synchronization and time division slot among a plurality of transferring units
US5283870A (en) * 1991-10-04 1994-02-01 Bull Hn Information Systems Inc. Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
US5412788A (en) * 1992-04-16 1995-05-02 Digital Equipment Corporation Memory bank management and arbitration in multiprocessor computer system
US5404464A (en) * 1993-02-11 1995-04-04 Ast Research, Inc. Bus control system and method that selectively generate an early address strobe
US5537555A (en) * 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US5630056A (en) * 1994-09-20 1997-05-13 Stratus Computer, Inc. Digital data processing methods and apparatus for fault detection and fault tolerance
US5590299A (en) * 1994-10-28 1996-12-31 Ast Research, Inc. Multiprocessor system bus protocol for optimized accessing of interleaved storage modules
US6446141B1 (en) 1999-03-25 2002-09-03 Dell Products, L.P. Storage server system including ranking of data source
US6735715B1 (en) 2000-04-13 2004-05-11 Stratus Technologies Bermuda Ltd. System and method for operating a SCSI bus with redundant SCSI adaptors
US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6633996B1 (en) 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6948010B2 (en) 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US7065672B2 (en) * 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
JP2004355271A (ja) * 2003-05-28 2004-12-16 Toshiba Corp データ転送システム
JP4765260B2 (ja) * 2004-03-31 2011-09-07 日本電気株式会社 データ処理装置およびその処理方法ならびにプログラムおよび携帯電話装置
JP4416694B2 (ja) * 2005-05-12 2010-02-17 株式会社ソニー・コンピュータエンタテインメント データ転送調停装置およびデータ転送調停方法
US8010764B2 (en) * 2005-07-07 2011-08-30 International Business Machines Corporation Method and system for decreasing power consumption in memory arrays having usage-driven power management

Family Cites Families (18)

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US3447135A (en) * 1966-08-18 1969-05-27 Ibm Peripheral data exchange
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system
US3997896A (en) * 1975-06-30 1976-12-14 Honeywell Information Systems, Inc. Data processing system providing split bus cycle operation
JPS5911980B2 (ja) * 1975-12-23 1984-03-19 日本電気株式会社 ランダムアクセスメモリソウチ
JPS52125243A (en) * 1976-04-14 1977-10-20 Fujitsu Ltd Memory access control system
US4130885A (en) * 1976-08-19 1978-12-19 Massachusetts Institute Of Technology Packet memory system for processing many independent memory transactions concurrently
US4128882A (en) * 1976-08-19 1978-12-05 Massachusetts Institute Of Technology Packet memory system with hierarchical structure
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
JPS5417643A (en) * 1977-07-08 1979-02-09 Mitsubishi Electric Corp Central processor
US4232366A (en) * 1978-10-25 1980-11-04 Digital Equipment Corporation Bus for a data processing system with overlapped sequences
US4280176A (en) * 1978-12-26 1981-07-21 International Business Machines Corporation Memory configuration, address interleaving, relocation and access control system
ES489424A0 (es) * 1979-03-12 1981-02-16 Digital Equipment Corp Perfeccionamientos introducidos en un aparato de tratamien- to de datos de informacion.
JPS57121746A (en) * 1981-01-22 1982-07-29 Nec Corp Information processing device
JPS57142441A (en) * 1981-02-26 1982-09-03 Isamu Iwase Solar-heat collecting apparatus
JPS592135A (ja) * 1982-06-28 1984-01-07 Nec Corp デ−タのブロツク転送方式
US4564899A (en) * 1982-09-28 1986-01-14 Elxsi I/O Channel bus
AU559558B2 (en) * 1982-06-30 1987-03-12 Elxsi I/o channel bus
US4494192A (en) * 1982-07-21 1985-01-15 Sperry Corporation High speed bus architecture

Also Published As

Publication number Publication date
EP0170021A2 (en) 1986-02-05
JPS6142049A (ja) 1986-02-28
US4669056A (en) 1987-05-26
DE3584402D1 (de) 1991-11-21
EP0170021A3 (en) 1988-05-25
EP0170021B1 (en) 1991-10-16
JPH0449144B2 (OSRAM) 1992-08-10

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Legal Events

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MKEX Expiry