CA1222835A - Shallow-junction semiconductor devices - Google Patents

Shallow-junction semiconductor devices

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Publication number
CA1222835A
CA1222835A CA000457570A CA457570A CA1222835A CA 1222835 A CA1222835 A CA 1222835A CA 000457570 A CA000457570 A CA 000457570A CA 457570 A CA457570 A CA 457570A CA 1222835 A CA1222835 A CA 1222835A
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CA
Canada
Prior art keywords
species
neutral
depth
approximately
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000457570A
Other languages
French (fr)
Inventor
Hyman J. Levinstein
David S. Yaney
Shyam P. Murarka
Michael J. Kelly
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AT&T Corp
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American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
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Publication of CA1222835A publication Critical patent/CA1222835A/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

SHALLOW-JUNCTION SEMICONDUCTOR DEVICES

Abstract A shallow-junction semiconductor device is fabricated by initially implanting a neutral species (non-doping impurity) into a surface region of a semiconductor body prior to the introduction of a dopant therein. This implant serves as a getter for defects and also as a physical barrier. The thermal diffusivity of subsequently introduced dopant species is thereby significantly reduced.
As a result, extremely shallow junctions are realized.

Description

" ~Z2~33~

SHALLOW-JUNCTION SEMICONDUCTOR DEVICES

Baclc~round of the Invention .___ ___________ __________ This invention relates to shallow-junction semi-conductor devices.
In various semiconductor devices, such as the metal-oxide-semiconductor field-effect transistor (MOSFET), it is desirable that a p-n junction of the device be as close to a substrate surface as possible. The present invention provides a means for obtaining p-n junctions which are significantly closer to a semiconductor body surface than was heretofore obtainable.
Summar~ of the Invention __ ___ ____ _ _ ___ _ __. ____ A neutral species is initially implanted into a surface region of a semiconductor body. In one example, the neutral species is implanted to form a layer whose maximum concentration occurs at a depth greater than that of a p~n junction to be subsequently formed. (In another example, the junction is subsequently established at a depth that is greater than the depth of the peak con centration of the neutral-species layer.) A dopant species is then implanted into the surface region at a depth less than the depth of the maximum-concentration of the previously implanted neutral species. Annealing to activate the dopant species is then ~arried out.
It is theorized that during this annealing step, the neutral-species layer serves to getter point defects in the body of the device. Additionally; this layer serves as a physical barrier to diffusion of dopant species. As a result, the diffusivity of the dopant species in the body is significantly lowered relative to the case in which no neutral-species layer is provided. In any event, the result is that a p-n junction i5 formed in the body of the device at an extremely shallow depth.

~2~ S
- la -In accordance with an aspect of the in~ention there is provided a shallow-~unction MOSFET device comprising a semiconductor body having field and gate portions on the surface of said body defining therebetween surface areas overlying spaced-apart source and drain regions of said device, a neutral-species layer of ions in said body in each of said regions having a profile whose peak concentration is at a predetermined depth below the surface of said body, said neutral-species layer oE ions beiny effective to limit the thermal diffusivity of active species in said body during establishment of p-n junctions therein, and spaced-apart p-n junctions in said body in said respective regions at a depth below said surface that is approximately one-tenth to two times that of said predetermined depth.
In accordance with another aspect of the invention there is provided a method of fabricating a MOSFET devise in a semiconductor body, comprising the steps of forming field and gate portions on the surface of said body to define therebetween surface areas overlying spaced-apart source and drain regions of said device, implanting a neutral species through said surface areas to form a neutral-species layer of ions having a peak concentration at a predetermined depth below each of said surface areas to limit the thermal diffusivity of active species in said body during establishment of a p-n junction in each of said regions; and introducing active species through said surface areas into sald body to establish spaced-apart p-n junctions in the respective regions of said body.
Brief Description of the Drawin~
FIGS. 1 through 4 are schematic representations of a portion of a MOSFET device at successive stages of a ~Z2~33S

fabrication sequence that embodies the principles of the present invention.
Detailed Descripti _ In accordance with this invention, shallow p-n junctions can be formed in a variety of semiconductor devices. These devices include, for example, p-n diodes, bipolar transistors and MOSFET devices. By way of example, the invention is described in connection with the provision of shallow p-n junctions in a MOSFET device.
A portion of such a MOSFET device at an intermediate stage of its fabrication cycle is shown in F~G. 1, such portion comprising a known gate-and-source-and -drain (GASAD) structure. The structure comprises a silicon body 10 having field-oxide ~silicon dioxide) portions 12, 14 thereon.
The structure further includes a gate-oxide (silicon dioxide) layer 16, a doped polysilicon layer 18, and a metallic~silicide (e.g. tantalum disilicide) layer 20. Also, the structure includes additional silicon dioxide layers 22,24. Openings 25, 26 are defined by the oxide layers 12, 22 and 14, 24. Source and drain regions are later formed in the body 10 in approximate alignment with these openings.
In accordance with the invention, a so-called neutral species is implanted into regions of body 10 defined by the openings 25, 26. Known ion implantation techniques can be used.
The term "neutral species" means ion species that do not produce active carriers in the semiconductor body and that are effective to limit the diffusivity of active species in the body. Such neutral species include carbon, oxygen/ argon or any other inert gas, Group IV elements such as silicon, germanium and tin, and nitrogen (minor activity).
Ions directed at the FIG. 2 structure are represented by arrows 28, the ions reaching the body 10 only through the openings 25, 26. In FIG. 2, the depth of
2~33~

the peak or maximum concentration of the approximately Gaussian-shaped distribution o~ the neutral-species lmplant in the body 10 is schematically depicted by lines 30 32 formed with x's.
~llustratively, the dosage of the neutral-species implant represented in FIG. 2 is selected to provide approximately one or two monolayers of the neutral species at the peak-concentration depth. Additionally, for the illustrative MOSFET device shown, the energy of the incident ions is selected such that the peak concentration of the implanted neutral species occurs approximately 2000 ~ below the surface of the body 10. In some devices, the peak concentration of the neutral-species implant is selected to occur at a depth greater than that of the p-n junction(s) to be subsequently formed in the body 10. In such devices, the depth of the subsequently formed p-n junction(s) is, for example, approximately one-tenth to three-quarters that of the depth of the peak concentration of the neutral species. (In other devices, described below, the depth of the p-n junction(s) is greater than the depth of the peak concentration of the neutral-species implant~) Various dosages and energies can be used. One set of dosage and energy values for the aforelisted neutral species is as follows: carbon, 5 x 1015 ions per ~quare centimeter (i/cm~), 80 kilo-electron-volts (keV);
oxygen, 5 x 1015 i/cm2, 80 keV; silicon, 5 x 1015 i/cm2, 150 keV; germanium, 5 x 1015 i/cm2~ 300 keV; tin, 5 x 1015 i/cm2, 400 keV;
argon, 5 x 1015 i/cm2, 180 keV; and nitrogen, 5 x 1015 i/c~2, 80 keV. For these values, the respective peak-concentration depth of each of the neutral species is approximately 2000 A below the surface of the body 10 shown in FIG. 2.
In some, but not necessarily all cases, the device structure represented in FIG. 2 is next subjected to an annealing step. ~For a subsequently introduced active species such as arsenic, it may actually be advantageous ~2Z~3~

not to anneal the implanted neutral species at this point in the Eabrication procedure.) In this annealing step, damage to the crystalline structure of the body 10 caused by the neutral-species implant is reduced. Further, the implanted species is stabilized and in effect locked in place in the body 10. Also, some gettering of defects and impurities in the body 10 typically occurs during this annealing step.
The annealing is done, for example, at a temperature in the range 700-to-~00 degrees Celsius in an inert ambient for about one-half hour. During annealing, no substantial vertical or lateral movement of the implanted neutral species occurs. Nor does any substantial movement occur later during the so-called activation annealing step described below.
Next, an active species is introduced into the structure by any of various known means, e.g., by ion implantation, as indicated by the arrows 34 in FIG. 3. The implanted active species comprisesr for example, a pentavalent p-type impurity such as arsenic, phosphorus or antimony, or a trivalent n-type impurity such as boron or gallium.
The depth of the peak or maximum concentration of the approximately Gaussian-shaped distribution of the active-species implant in the body 10 is schematically represented in FIG. 3 by lines 36, 38 formed with dots.
The peak concentration of the implanted active species is selected to occur relatively close to the top surface of the body 10, e.g., at a depth of approximately 200 to-100o ~.
More specifically, for a carbon neutral species implant having a peak-concentration depth 30, 32 ~FIG. 3) of about 2000 A, an arsenic implant having a peak-concentration depth 36, 38 of approximately 200 A is achieved by implanting 4 x 1015 i/cm2 at 30 keV. For a carbon or nitrogen implant having a peak-concentration depth 30, 32 (FIG. 3) of about 2000 A, a boron implant 22835i having a peak-concentration depth 36, 38 of approximately 1000 A is achieved by implanting 4 x 1015 i/cm2 at 30 keV.
Subsequently, standard activation annealing of the second-implanted or active dopant species is carried out.
During this step, ît is believed that gettering of point defects and metallic impurities occurs in the body 10. It appears also that, because of this gettering action, the thermal diffusivity of the active species is substantially reduced relative to what it would have been in the absence of the neutral-species implant. Additionally, it appears that the priorly formed neutral-species implant serves as a physical barrier against diffusion of the active species.
However, regardless of the physical phenomena involved, the result of the described process is that the p-n junction formed by the active-species implant occurs at a depth far less than it would have been if the neutral-species implant had not been present. Extremely shallow p-n junctions are thereby formed.
For an active species implant of arsenic, activation annealing is carried out at, for examyle, abou~
1000 degrees Celsius for approximately three hours in a standard mildly dry oxidi2ing atmosphere. The resulting p-n junction is at a depth of approximately 1400 A. Without the priorly implanted neutral-species, but with all other processing conditions approximately the same, the p-n junction is at a depth of about 3700 ~.
For an active-species implant of boron, activation annealina is carried out at/ for example, about 900 degrees Celsius for approximately five hours in a standard mildly dry oxidizing atmosphere. The p-n junction occurs at approximately 3300 A. Without the presence of the neutral-species implant, but with all other processing conditions approximately the same, the p-n junction occurs at a depth of about 6700 A.
In the example above in which the active species comprises arsenic, the p-n junction is at a depth less than 3r~

the depth of the peak concentration of an lmplanted neutral species layer. Conversely, in the example above in which the active species comprises boron, the p-n junction is at a depth greater than the depth of the peak concentration of the implanted neutral-species layer. In general, it is feasible to form p-n junctions at a depth in the range of approximately one-tenth to two times the depth of the peak concentration of the implanted neutral-species layer.
It is possible to form the p-n junction at a depth less than the depth of the peak concentration of the implanted neutral-species layer or in a number of ways. For example~ the active impurity species can be initially introduced into the device structure at a shallower depth than specified above for boron and/or by activation annealing the structure at a lower temperature than specified above. Or the peak concentration of the neutral-species layer can be initially formed sufficiently deep that, after annealing, the junction is established at a depth less than the depth of the peak concentration of the neutral-species layer.

Claims (19)

Claims
1. A shallow-junction MOSFET device comprising a semiconductor body having field and gate portions on the surface of said body defining therebetween surface areas overlying spaced-apart source and drain regions of said device, a neutral-species layer of ions in said body in each of said regions having a profile whose peak concentration is at a predetermined depth below the surface of said body, said neutral-species layer of ions being effective to limit the thermal diffusivity of active species in said body during establishment of p-n junctions therein, and spaced-apart p-n junctions in said body in said respective regions at a depth below said surface that is approximately one-tenth to two times that of said predetermined depth.
2. A device as in claim 1 wherein said neutral species is selected from the group consisting of carbon, oxygen, silicon, germanium, tin, an inert gas and nitrogen.
3. A device as in claim 2 wherein said p-n junction is established in said body at a depth that is approximately one-tenth to three-quarters that of the depth of the peak concentration of said neutral species.
4. A shallow-junction MOSFET device comprising a semiconductor body having field and gate portions on the surface of said body defining therebetween spaced-apart surface areas overlying source and drain regions of said device, a neutral-species layer of ions in said body in each of said regions formed by ion implantation through said surface areas of said body to form a peak concentration of neutral species at a predetermined depth in each of said regions, said neutral species layer of ions being effective to limit the thermal diffusivity of active species in said body during establishment of p-n junctions therein, and p-n junctions in said body in said respective regions formed by introducing active species through said surface areas to establish said junctions at depths in the range of approximately one-tenth to two times said predetermined depth.
5. A device as in claim 4 wherein said neutral species is selected from the group consisting of carbon, oxygen, silicon, germanium, tin, an inert gas and nitrogen.
6. A device as in claim 5 wherein the peak concentraction of said neutral-species layer is approximately 2000 .ANG. below said surface and said junction is approximately 1400 .ANG. below said surface.
7. A method of fabricating a MOSFET device in a semiconductor body, comprising the steps of forming field and gate portions on the surface of said body to define therebetween surface areas overlying spaced-apart source and drain regions of said device, implanting a neutral species through said surface areas to form a neutral-species layer of ions having a peak concentration at a predetermined depth below each of said surface areas to limit the thermal diffusivity of active species in said body during establishment of a p-n junction in each of said regions, and introducing active species through said surface areas into said body to establish spaced-apart p-n junctions in the respective regions of said body.
8. A method as in claim 7 wherein said body is annealed after introduction of said active species therein to activate said active species, and wherein the peak concentration of the active species is established, before annealing, at a depth that is less than the depth of the peak concentration of said neutral-species layer of ions.
9. A method as in claim 8 wherein said junction is established after annealing at a depth in the range of approximately one-tenth to two times said predetermined depth.
10. A method as in claim 9 wherein said neutral species is selected from the group consisting of carbon, oxygen, silicon, germanium, tin, an inert gas and nitrogen.
11. A method as in claim 10 wherein said body comprises n-type silicon and said active species comprises a pentavalent impurity.
12. A method as in claim 11 wherein said active species is selected from the group consisting of arsenic, phosphorus and antimony.
13. A method as in claim 10 wherein said body comprises p-type silicon and said active species comprises a trivalent impurity.
14. A method as in claim 13 wherein said active species is selected from the group consisting of boron and gallium.
15. A method as in claim 11 wherein said activation annealing step is carried out in the temperature range of approximately 900 to 1050 degrees Celsius in a mildly oxidizing atmosphere.
16. A method as in claim 10 further including the step of annealing said body after said neutral-species implant step and before said activation annealing step.
17. A method as in claim 16 wherein the annealing step before activation annealing is carried out at a temperature in the range of about 700-to-900 degrees Celsius in an inert ambient for approximately one-half hour.
18. A device as in claim 2 wherein said neutral-species layer of ions comprises approximately one or two monolayers of the neutral-species ions at the peak-concentration depth.
19. A device as in claim 5 wherein said neutral species layer of ions comprises approximately one or two monolayers of the neutral-species ions at the peak-concentration depth.
CA000457570A 1983-07-25 1984-06-27 Shallow-junction semiconductor devices Expired CA1222835A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51675583A 1983-07-25 1983-07-25
US516,755 1995-08-18

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CA1222835A true CA1222835A (en) 1987-06-09

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EP (1) EP0151585A4 (en)
JP (1) JPS60501927A (en)
CA (1) CA1222835A (en)
WO (1) WO1985000694A1 (en)

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US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
US5654209A (en) * 1988-07-12 1997-08-05 Seiko Epson Corporation Method of making N-type semiconductor region by implantation
EP0350845A3 (en) * 1988-07-12 1991-05-29 Seiko Epson Corporation Semiconductor device with doped regions and method for manufacturing it
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JPH05190849A (en) * 1992-01-14 1993-07-30 Oki Electric Ind Co Ltd Manufacture of semiconductor device
KR970072066A (en) * 1996-04-29 1997-11-07 윌리엄 비. 켐플러 How to optimize the sub-amorphous threshold amount implantation energy used prior to dopant implantation to achieve shallower junctions
WO1997042652A1 (en) * 1996-05-08 1997-11-13 Advanced Micro Devices, Inc. Control of junction depth and channel length using generated interstitial gradients to oppose dopant diffusion
US6051460A (en) * 1997-11-12 2000-04-18 Advanced Micro Devices, Inc. Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon
US6013546A (en) * 1997-12-19 2000-01-11 Advanced Micro Devices, Inc. Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
US6146934A (en) * 1997-12-19 2000-11-14 Advanced Micro Devices, Inc. Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
US6087209A (en) * 1998-07-31 2000-07-11 Advanced Micro Devices, Inc. Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant
FR2828331A1 (en) * 2001-07-31 2003-02-07 St Microelectronics Sa METHOD FOR MANUFACTURING BIPOLAR TRANSISTOR IN A CMOS INTEGRATED CIRCUIT

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WO1985000694A1 (en) 1985-02-14
EP0151585A1 (en) 1985-08-21
EP0151585A4 (en) 1986-02-20
JPS60501927A (en) 1985-11-07

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