CA1218161A - Direct memory access controller - Google Patents
Direct memory access controllerInfo
- Publication number
- CA1218161A CA1218161A CA000471896A CA471896A CA1218161A CA 1218161 A CA1218161 A CA 1218161A CA 000471896 A CA000471896 A CA 000471896A CA 471896 A CA471896 A CA 471896A CA 1218161 A CA1218161 A CA 1218161A
- Authority
- CA
- Canada
- Prior art keywords
- data
- memory
- cpu
- random access
- format
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
- Dram (AREA)
Abstract
Abstract of the Disclosure An arrangement to couple at least one I/O device to the main bus between a CPU and a main memory in a digital computer system is shown to include a random access memory made up of a dedicated part of the main memory and control circuitry to allow access between addresses in the random access memory and either the CPU or the at least one I/O device, such circuitry being arranged to give priority of access to the CPU except when data is actually being transferred from the I/O device and the random access memory.
Description
By Background of -the Invention This invention pertains generally to digital completers and in particular to a direct memory address (Do) system for linking peripheral devices to such a computer, As is known, a digital computer may be equipped with a DAM capability to allow various types of input/output devices (I/O devices) to be connected, usually over a shared memory bus.
Unfortunately, the use of a shared memory bus requires that the operation of the central processing unit CUP of the computer be temporarily halted whenever data is to be passed to (or from) an I/O module. Obviously, if there are many I/O modules connected in the system, the frequency of these interruptions may be so great that the efficiency of the system is degraded to an unacceptable degree.
It is known that I/O devices may be connected to a computer system through arrangements including a buffer memory.
For example, as shown and described, a magnetic drum is arranged so as to be accessible independently to the CPU of a computer system and to a selected one of a plurality of I/O devices. While such an arrangement is useful in many "low speed" applications in which interruption of the CPJ are of little moment, the time required to access any given address is too long to allow use in "high speed" applications in which the frequency and duration of CPU interruption must be reduced to a minimum.
~18~
Summary of the Invention With the foregoing background of the invention in mind it is an object of this invention to provide a DAM system for a digital computer wherein CPU interruptions are reduced to a minimum.
It is another object of -this invention to provide a MA
system for a digital computer that obviates any requirement for contention among various I/O modules.
It is yet another object of this invention to provide a DOW system for a digital computer wherein each Dry controller is required to address only a limited portion of CPU memory, thus reducing the complexity of the DAM controller.
These and other objects of this invention are generally attained by providing a digital computer system having a plurality of I/O modules interposed between the CPU of such system and I/O devices. Each I/O module includes a ala controller and a random access buffer memory formed from a dedicated main Emory of the computer system.
~Z~B~l More particularly, the invention provides a digital computer system for processing data in a serial or parallel format wherein a CPU is connected over a main bus to a main memory and data in serial or parallel format is also connected to such bus from at least one I/O device through an I/O module, the data to be processed being included in digital words that also include coded command signals indicative of the format of the data and the desired direction of transmission of the data and memory addresses, the I/O module comprising: (a) a control logic network, responsive to the coded command signal from the CPU and the coded command signal from the I/O device, for producing enabling signals indicative of the format of the data, and a selected one of the memory addresses in a first part of the main memory, such control logic network being responsive to the coded command signal from the CPV in all cases except when the coded command signal from the l/O device indicates that data is being passed through the switching means from the I/O device to the random access memory; (b) a random access memory, such memory being the first part of the main memory; (c) memory addressing means, responsive to the enabling signal indict-live of the selected one of the memory addresses for selectively addressing the random access memory; and (d) switching means, responsive to the enabling signals indicative of the format of the data and the desired direction of transmission of the data, for connecting the CPU or the I/O device to the selected address in the random access memory.
- pa -Brief Description of the Drawings other objects and many of the attendant advantages of this invention will be readily appreciated as the same become better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:
Fir,. 1 is a simplified block diagram of a data processing system according to this invention; and FIG. 2 is a simplified bloc diagram illustrating the data flow within the I/O module of FIG. 1.
12~
Description of the Preferred Embo2ime~t Before proceeding with a detailed exposition or a data processing system according to this invention, it should be noted that the invention lies in an improved module inter-posed between the CPIJ of a digital computer and an I/O
device. Since this is so, it is felt that a general descrip-lion of the architecture of a complete digital computer and a detailed description of known elements (such as clock Zen-orators and read/write mechanisms) is not required to enable a person of ordinary skill in the art to practice the invention.
In addition, because the invention may be used with any known types of I/O devices, any known kind of memory device used in a digital computer as main memory and serial or parallel processing, the elements making up the contemplated module are shown in block form, it being understood that each such element is known, per so. Finally, it should be noted that only a single I/O module and remote I/O device are illustrated although any number ox remote I/O devices may be accommodated providing, however, that the I/O module has a sufficient number ox channels.
Referring now to FIX.. 1 it may be seen that an I/O
module 15 is connected in a conventional manner to the main bus (not numbered of a digital computer snot numbered between a CUT 11 and a main memory 13. An interface unit 19 of known construction is connected between the I/O module 15 ~Z~8~1 and an I/O device 17. It will be appreciated that the inter-face unit 19 is provided to convert the format of data to and from the particular type of I/O device 17 being used to the format of the data on the main bus (not numbered) and in the main memory 13. thus, depending upon the particular I/O
device, the interface unit 19 may include analos-to-digital converters, digital-to-analog converters and serial-to-parallel converters. It will also be appreciated that, whether the format of each word of the data on the main bus is serial or parallel, each word has an address field, a command field and a data field (here designated as being on buses marked, respectively, as "CPU ADDRESS BUS," "CPU
Coronado RIPS" and ~lcprJ DATA US." It will also be appreciated that other signals such as clock pulses and read/write command signals) required for operation but not for an understanding of the invention are passed over the main bus (not numbered). Finally, and most importantly, it will be noted that, as shown in broken line, a dedicated section of the main memory 13 is here used as a random access memory (RAM 21) in the I/O module 15 and that different dedicated sections of the main memory 13 are used for any other I/O
modules connected to the main bus.
Before referring to FIG. 2 in detail it will be noted that the elements within the IT module 15 are by and large shown to be "hard-wired" through switching arrangements. It .
I
will become apparent, however, that the various elements could be "addressable" units to eliminate to various slush-in arrangements. Turning now to FIG. 2, the I module 15 is shown to include a random access memory 21, consisting of ; a dedicated section of the main memory 13 (FIG. 1). address-in of the RAM 21 is effected from either the CPU ADDRESS GUS
(not numbered) or through any one of four elements, DAM 23, 25, 27, 29 (Model AMY devices from AND, (Advanced Micro Devices, Inc.), 901 Thompson Place, Sunnyvale, California) in a manner to be described. Data to be written in (or read out of) the RAM 21 is extant on the buses marked DATA BUS "A" or DATA
BUS "B".
To effect the foregoing, any extant CPU COMMAND and I/O
COMMAND are applied to a control logic network 31, here a conventional logic matrix responsive to either, or both, of the applied commands to: (a) address the RAM 21 through one of the DAM 23, 25, 27, 29 or (in a manner to be described) by the CPU ADDRESS; (b) write (in a manner to be described) serial data derived from either the I/O device 17 (FIG. 1) over DATA BUS "A" or the CPU DATA BUS (FIG. 1) over DATA BUS
"B" at the selected address in the RAM 21; (c) read serial data at the selected address in the RAM 21 and ultimately pass such data (over DATA BUS "A" or DATA BUS "B") to the I/O device 17 (FIG. 1) or to the CPU DATA BUS to the CPU 11 FIG. l); or (d) pass parallel data from the CPU DATA BUS
I
to the I/O device 17 (FIG. 1). In connection with the foregoing, it should be noted that the control logic network 31 is arranged to give priority to the CPU COMMAND except in the single case wherein data from the I/O device 17 (FIG. 1) is in the process of being written in the RAM 21 and access to the RAM 21 is commanded by the CPU COMMAND. In only such case (which would occur but rarely) an interrupt of comma-nication with the CPU 11 FIG. 1) occurs.
A SERIAL ENABLE or a PARALLEL ENABLE signal is passed as shown from the control logic network 31 to, respectively, a serial communication controller 33 or a parallel communique-lion controller 35 to enable one or the other. The serial communication controller 33 is a Model ZOO from ZILOG, Inc., Dell Avenue, Campbell, California 95008. The parallel commune-cation controller 35 is a model AMOEBA device from AND.
The CPU DATA BUS (FIG. 1) is connected to a CPU DATA
BUFFER 37 (here a Model AMOEBA device from Advanced Micro Devices, Inc., 401 Thompson Place, Sunnyvale, California) and the CPU ADDRESS BUS FIG. 1) is connected to two buffers designated respectively as CPU ADDRESS BUFFER (SERIES) 39 and CPU ADDRESS BUFFET (PARALLEL) 41. The two just-mentioned buffers are yodel 54LS244 devices from Texas Instruments, Inc., Dallas, Texas 75222. It will be noted that the buffers 39, 41 are addressable, meaning that the particular CPU address extant at any time determines which of the two may be enabled.
~181~L
Interposed between the RAM 21, the CPU DATA BUFFER 37, the serial communication controller 33 and the parallel coy-monkeyshine controller 35 are buffers aye, 43b and switches aye, 45b, 47. The buffers aye, 43b are Model AMOEBA devices from Advanced Micro Devices, Inc. It will be appreciated that each one of the buffers aye, 43b is an eight-bit device and, therefore, that the two together accommodate 16 bit words on DATA BUS "A". The switches aye, 45b connect, in accordance with actuating signal "a" out of the control logic network 31, either the serial communication controller 33 or the parallel communication controller 35 to the buffers aye, 43b. The switch 47 connects, in accordance with actuating signal "b" out of the control logic network 31, either the buffers aye, 43b or the CPU DATA BUFFER 37 to the RAM 21.
To complete the description, switches aye, 49b and a read/write controller (Row 51), each responsive to control signals as indicated out of the control logic network 31, allow addressing of DAM 27 and DAM 29 (if parallel data is to be passed to or from RAM 21) and recording or reading of data at a selected address (Al, A, A, A) in the RAM 21.
Having described a layout of an exemplary I/O module, it will now be apparent that the listed objects of this invention are met. Thus, because the control logic network 31 is arranged to give the CPU COMMAND priority (except when an I/O COMMAND is actually being executed), the number of CPV
_ g _ I
interruptions is reduced to a minimum. Because the AYE 21 in each one of the different I/O modules is a separate dedicated part of the main memory 13 (FIG. 1), there is no need for contention among I modules. The DAM controllers need only address the Rat 21, rather than the entire CPIJ memory, thus reducing the controller's complexity.
It will now be apparent that changes may be made without departing from the inventive concepts. For example, if the I/O module is to be used in a digital computer system wherein only serial data is to be processed r the elements required for parallel data may be eliminated. Similarly, if the digital computer system processes only parallel data, the elements required for serial data may be eliminated. It is felt, therefore, that this invention should not be restricted to the disclosed embodiment, but rather should be limited only by the spirit and scope of the appended claims.
Unfortunately, the use of a shared memory bus requires that the operation of the central processing unit CUP of the computer be temporarily halted whenever data is to be passed to (or from) an I/O module. Obviously, if there are many I/O modules connected in the system, the frequency of these interruptions may be so great that the efficiency of the system is degraded to an unacceptable degree.
It is known that I/O devices may be connected to a computer system through arrangements including a buffer memory.
For example, as shown and described, a magnetic drum is arranged so as to be accessible independently to the CPU of a computer system and to a selected one of a plurality of I/O devices. While such an arrangement is useful in many "low speed" applications in which interruption of the CPJ are of little moment, the time required to access any given address is too long to allow use in "high speed" applications in which the frequency and duration of CPU interruption must be reduced to a minimum.
~18~
Summary of the Invention With the foregoing background of the invention in mind it is an object of this invention to provide a DAM system for a digital computer wherein CPU interruptions are reduced to a minimum.
It is another object of -this invention to provide a MA
system for a digital computer that obviates any requirement for contention among various I/O modules.
It is yet another object of this invention to provide a DOW system for a digital computer wherein each Dry controller is required to address only a limited portion of CPU memory, thus reducing the complexity of the DAM controller.
These and other objects of this invention are generally attained by providing a digital computer system having a plurality of I/O modules interposed between the CPU of such system and I/O devices. Each I/O module includes a ala controller and a random access buffer memory formed from a dedicated main Emory of the computer system.
~Z~B~l More particularly, the invention provides a digital computer system for processing data in a serial or parallel format wherein a CPU is connected over a main bus to a main memory and data in serial or parallel format is also connected to such bus from at least one I/O device through an I/O module, the data to be processed being included in digital words that also include coded command signals indicative of the format of the data and the desired direction of transmission of the data and memory addresses, the I/O module comprising: (a) a control logic network, responsive to the coded command signal from the CPU and the coded command signal from the I/O device, for producing enabling signals indicative of the format of the data, and a selected one of the memory addresses in a first part of the main memory, such control logic network being responsive to the coded command signal from the CPV in all cases except when the coded command signal from the l/O device indicates that data is being passed through the switching means from the I/O device to the random access memory; (b) a random access memory, such memory being the first part of the main memory; (c) memory addressing means, responsive to the enabling signal indict-live of the selected one of the memory addresses for selectively addressing the random access memory; and (d) switching means, responsive to the enabling signals indicative of the format of the data and the desired direction of transmission of the data, for connecting the CPU or the I/O device to the selected address in the random access memory.
- pa -Brief Description of the Drawings other objects and many of the attendant advantages of this invention will be readily appreciated as the same become better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:
Fir,. 1 is a simplified block diagram of a data processing system according to this invention; and FIG. 2 is a simplified bloc diagram illustrating the data flow within the I/O module of FIG. 1.
12~
Description of the Preferred Embo2ime~t Before proceeding with a detailed exposition or a data processing system according to this invention, it should be noted that the invention lies in an improved module inter-posed between the CPIJ of a digital computer and an I/O
device. Since this is so, it is felt that a general descrip-lion of the architecture of a complete digital computer and a detailed description of known elements (such as clock Zen-orators and read/write mechanisms) is not required to enable a person of ordinary skill in the art to practice the invention.
In addition, because the invention may be used with any known types of I/O devices, any known kind of memory device used in a digital computer as main memory and serial or parallel processing, the elements making up the contemplated module are shown in block form, it being understood that each such element is known, per so. Finally, it should be noted that only a single I/O module and remote I/O device are illustrated although any number ox remote I/O devices may be accommodated providing, however, that the I/O module has a sufficient number ox channels.
Referring now to FIX.. 1 it may be seen that an I/O
module 15 is connected in a conventional manner to the main bus (not numbered of a digital computer snot numbered between a CUT 11 and a main memory 13. An interface unit 19 of known construction is connected between the I/O module 15 ~Z~8~1 and an I/O device 17. It will be appreciated that the inter-face unit 19 is provided to convert the format of data to and from the particular type of I/O device 17 being used to the format of the data on the main bus (not numbered) and in the main memory 13. thus, depending upon the particular I/O
device, the interface unit 19 may include analos-to-digital converters, digital-to-analog converters and serial-to-parallel converters. It will also be appreciated that, whether the format of each word of the data on the main bus is serial or parallel, each word has an address field, a command field and a data field (here designated as being on buses marked, respectively, as "CPU ADDRESS BUS," "CPU
Coronado RIPS" and ~lcprJ DATA US." It will also be appreciated that other signals such as clock pulses and read/write command signals) required for operation but not for an understanding of the invention are passed over the main bus (not numbered). Finally, and most importantly, it will be noted that, as shown in broken line, a dedicated section of the main memory 13 is here used as a random access memory (RAM 21) in the I/O module 15 and that different dedicated sections of the main memory 13 are used for any other I/O
modules connected to the main bus.
Before referring to FIG. 2 in detail it will be noted that the elements within the IT module 15 are by and large shown to be "hard-wired" through switching arrangements. It .
I
will become apparent, however, that the various elements could be "addressable" units to eliminate to various slush-in arrangements. Turning now to FIG. 2, the I module 15 is shown to include a random access memory 21, consisting of ; a dedicated section of the main memory 13 (FIG. 1). address-in of the RAM 21 is effected from either the CPU ADDRESS GUS
(not numbered) or through any one of four elements, DAM 23, 25, 27, 29 (Model AMY devices from AND, (Advanced Micro Devices, Inc.), 901 Thompson Place, Sunnyvale, California) in a manner to be described. Data to be written in (or read out of) the RAM 21 is extant on the buses marked DATA BUS "A" or DATA
BUS "B".
To effect the foregoing, any extant CPU COMMAND and I/O
COMMAND are applied to a control logic network 31, here a conventional logic matrix responsive to either, or both, of the applied commands to: (a) address the RAM 21 through one of the DAM 23, 25, 27, 29 or (in a manner to be described) by the CPU ADDRESS; (b) write (in a manner to be described) serial data derived from either the I/O device 17 (FIG. 1) over DATA BUS "A" or the CPU DATA BUS (FIG. 1) over DATA BUS
"B" at the selected address in the RAM 21; (c) read serial data at the selected address in the RAM 21 and ultimately pass such data (over DATA BUS "A" or DATA BUS "B") to the I/O device 17 (FIG. 1) or to the CPU DATA BUS to the CPU 11 FIG. l); or (d) pass parallel data from the CPU DATA BUS
I
to the I/O device 17 (FIG. 1). In connection with the foregoing, it should be noted that the control logic network 31 is arranged to give priority to the CPU COMMAND except in the single case wherein data from the I/O device 17 (FIG. 1) is in the process of being written in the RAM 21 and access to the RAM 21 is commanded by the CPU COMMAND. In only such case (which would occur but rarely) an interrupt of comma-nication with the CPU 11 FIG. 1) occurs.
A SERIAL ENABLE or a PARALLEL ENABLE signal is passed as shown from the control logic network 31 to, respectively, a serial communication controller 33 or a parallel communique-lion controller 35 to enable one or the other. The serial communication controller 33 is a Model ZOO from ZILOG, Inc., Dell Avenue, Campbell, California 95008. The parallel commune-cation controller 35 is a model AMOEBA device from AND.
The CPU DATA BUS (FIG. 1) is connected to a CPU DATA
BUFFER 37 (here a Model AMOEBA device from Advanced Micro Devices, Inc., 401 Thompson Place, Sunnyvale, California) and the CPU ADDRESS BUS FIG. 1) is connected to two buffers designated respectively as CPU ADDRESS BUFFER (SERIES) 39 and CPU ADDRESS BUFFET (PARALLEL) 41. The two just-mentioned buffers are yodel 54LS244 devices from Texas Instruments, Inc., Dallas, Texas 75222. It will be noted that the buffers 39, 41 are addressable, meaning that the particular CPU address extant at any time determines which of the two may be enabled.
~181~L
Interposed between the RAM 21, the CPU DATA BUFFER 37, the serial communication controller 33 and the parallel coy-monkeyshine controller 35 are buffers aye, 43b and switches aye, 45b, 47. The buffers aye, 43b are Model AMOEBA devices from Advanced Micro Devices, Inc. It will be appreciated that each one of the buffers aye, 43b is an eight-bit device and, therefore, that the two together accommodate 16 bit words on DATA BUS "A". The switches aye, 45b connect, in accordance with actuating signal "a" out of the control logic network 31, either the serial communication controller 33 or the parallel communication controller 35 to the buffers aye, 43b. The switch 47 connects, in accordance with actuating signal "b" out of the control logic network 31, either the buffers aye, 43b or the CPU DATA BUFFER 37 to the RAM 21.
To complete the description, switches aye, 49b and a read/write controller (Row 51), each responsive to control signals as indicated out of the control logic network 31, allow addressing of DAM 27 and DAM 29 (if parallel data is to be passed to or from RAM 21) and recording or reading of data at a selected address (Al, A, A, A) in the RAM 21.
Having described a layout of an exemplary I/O module, it will now be apparent that the listed objects of this invention are met. Thus, because the control logic network 31 is arranged to give the CPU COMMAND priority (except when an I/O COMMAND is actually being executed), the number of CPV
_ g _ I
interruptions is reduced to a minimum. Because the AYE 21 in each one of the different I/O modules is a separate dedicated part of the main memory 13 (FIG. 1), there is no need for contention among I modules. The DAM controllers need only address the Rat 21, rather than the entire CPIJ memory, thus reducing the controller's complexity.
It will now be apparent that changes may be made without departing from the inventive concepts. For example, if the I/O module is to be used in a digital computer system wherein only serial data is to be processed r the elements required for parallel data may be eliminated. Similarly, if the digital computer system processes only parallel data, the elements required for serial data may be eliminated. It is felt, therefore, that this invention should not be restricted to the disclosed embodiment, but rather should be limited only by the spirit and scope of the appended claims.
Claims
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a digital computer system for processing data in a serial or parallel format wherein a CPU is connected over a main bus to a main memory and data in serial or parallel format is also connected to such bus from at least one I/O device through an I/O module, the data to be processed being included in digital words that also include coded command signals indicative of the format of the data and the desired direction of transmission of the data and memory addresses, the I/O module comprising: (a) a control logic network, responsive to the coded command signal from the CPU and the coded command signal from the I/O device, for producing enabling signals indicative of the format of the data, and a selected one of the memory addresses in a first part of the main memory, such control logic network being responsive to the coded command signal from the CPU in all cases except when the coded command signal from the I/O device indicates that data is being passed through the switching means from the I/O device to the random access memory; (b) a random access memory, such memory being the first part of the main memory; (c) memory addressing means, responsive to the enabling signal indicative of the selec-ted one of the memory addresses for selectively addressing the random access memory; and (d) switching means, responsive to the enabling signals indicative of the format of the data and the desired direction of transmission of the data, for connecting the CPU or the I/O device to the selected address in the random access memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US57279984A | 1984-01-23 | 1984-01-23 | |
| US572,799 | 1984-01-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1218161A true CA1218161A (en) | 1987-02-17 |
Family
ID=24289398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000471896A Expired CA1218161A (en) | 1984-01-23 | 1985-01-11 | Direct memory access controller |
Country Status (4)
| Country | Link |
|---|---|
| CA (1) | CA1218161A (en) |
| DE (1) | DE3501997C2 (en) |
| FR (1) | FR2558616B1 (en) |
| GB (1) | GB2153119B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4271466A (en) * | 1975-02-20 | 1981-06-02 | Panafacom Limited | Direct memory access control system with byte/word control of data bus |
| US4075691A (en) * | 1975-11-06 | 1978-02-21 | Bunker Ramo Corporation | Communication control unit |
| JPS533029A (en) * | 1976-06-30 | 1978-01-12 | Toshiba Corp | Electronic computer |
| JPS5454540A (en) * | 1977-10-11 | 1979-04-28 | Hitachi Ltd | Data buscontrol system |
| IT1091633B (en) * | 1977-12-30 | 1985-07-06 | Olivetti C Ing E C Spa | DEVICE FOR THE MANAGEMENT OF DIRECT ACCESS TO THE MEMORY OF A COMPUTER |
| JPS5789128A (en) * | 1980-11-25 | 1982-06-03 | Hitachi Ltd | Controlling system for information interchange |
| US4543627A (en) * | 1981-12-14 | 1985-09-24 | At&T Bell Laboratories | Internal communication arrangement for a multiprocessor system |
-
1985
- 1985-01-11 CA CA000471896A patent/CA1218161A/en not_active Expired
- 1985-01-22 GB GB08501598A patent/GB2153119B/en not_active Expired
- 1985-01-22 DE DE19853501997 patent/DE3501997C2/en not_active Expired - Lifetime
- 1985-01-23 FR FR8500918A patent/FR2558616B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2153119B (en) | 1987-12-09 |
| GB2153119A (en) | 1985-08-14 |
| FR2558616A1 (en) | 1985-07-26 |
| GB8501598D0 (en) | 1985-02-20 |
| DE3501997C2 (en) | 1996-03-14 |
| DE3501997A1 (en) | 1985-07-25 |
| FR2558616B1 (en) | 1988-12-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |