DE3501997A1 - DIGITAL COMPUTING DEVICE WITH DIRECT MEMORY ADDRESSING BY PERIPHERAL DEVICES - Google Patents

Description

~~ Lawyer files .: 27 - Pat. 363

RAYTHEON COMPANY, 141 Spring Street, Lexington, Mass. 02173, United States of America

Digital computing device with direct memory addressing by peripheral devices

The invention relates generally to digital computing devices and, more particularly, to a system with direct memory addressing for coupling peripheral devices to the computing device.

It is known that a digital computing device is equipped with the possibility of direct memory addressing can be used to connect different types of input / output devices, generally via a shared memory bus, to be able to connect. Unfortunately, the use of a shared memory bus requires that the Operation of the central data processing unit of the computer must be briefly interrupted as soon as data after a Input / output module transferred or entered from there Need to become. When a variety of input / output modules is connected to the system, the frequency of these interruptions can obviously be so great that the Profitability of the system deteriorates or even in is unacceptably degraded ..

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Egg. It is also known that input / output devices can be connected to a computer system via arrangements which contain a buffer memory. As shown and explained in the literature, for example, a magnetic drum store can be designed so that it is accessible independently of one another for a central data processing unit of a computer and for a particular one of a plurality of input / output devices. Although such an arrangement is useful in many cases, it is a question of comparatively low operating speed applications in which interruptions in the work of the central data processing unit play a minor role, but in these known systems the time for access to a specific address is too long in order to use such systems for high operating speeds, at which the frequency and the duration of the respective interruption of the operation of the central data processing unit must be kept to a minimum.

The aim of the invention is to solve the problem, in systems with direct memory addressing through input / : Output devices in digital computing devices interrupt the operation of the central data processing unit j to a minimum. In doing so, the need should

ι a preference or disadvantage or a valuation of the

Interests of the various input / output modules completely be avoided. A control device for direct memory addressing should only cover a limited portion of the memory the central data processing unit each address; must be reduced, which changes the structure of the control device to simplify direct memory addressing.

The above object is achieved with a digital

ι Computing device with direct memory addressing through input

output and output devices according to the invention solved in that one each between the central data processing unit and a certain number of input / output devices

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, An / .ihl of input / output modules is provided that

\ One control device each for direct memory address
! and a buffer memory with random access
I contain the one assigned to the module in question
\ Part of a main memory of the digital computing device
is formed.

Advantageous refinements and developments of such
! digital computing devices are also the subject of the dem

Claim 1 subordinate claims, the content of which hereby
: is expressly made part of the description,

; without repeating the wording at this point.

In the following an embodiment with reference to
! the drawing explained in more detail. In this represent:!

i;

i Fig. 1 is a simplified block diagram of a!

! I.

I digital computing device, where the j

: Data processing in the present

specified manner and;

1 ί

i I

ί Fig. 2 is a simplified block diagram for j

Clarification of the data flow within '

half of an input / output module of the
Circuit according to Figure 1.

Before a detailed description of a data processing system of the type specified here, it should be pointed out that
that the peculiarity of the system discussed here
a module or a structural unit concentrated, which is arranged between the 'central data processing unit of a digital computing ' device and an input / output device. ! - Due to this fact, it is not necessary for a person skilled in the art to provide a general description of the
Architecture of a complete digital computer and a detailed description of the known components,

ORIGINAL BATHROOM ^:

". '· KLimpuls ^. Ι: iren un.'l read / write control i · .lines, to carry out. According to the principles given here, also in connection with any known types of

; Input / output devices, in conjunction with any known Storage devices for digital computers, e.g. main memory, as well as for serial processing and parallel processing

¹ processing, it should be sufficient to list the components that make up the input / output module under consideration as, for example, in each case

'' to represent known elements in block symbols. Further it can be seen that in the illustrated embodiment only a single input / output module and an associated remote one or peripheral input / output device shown

ι, but any number of remote input / Output devices, provided that the relevant

: fende input / output module a sufficient number of

; Has channels.

Looking now at Figure 1, it can be seen that an input / output module 15 in a conventional manner with a no closer designated main bus is connected to a digital computing device, also not designated in detail, this main bus between a central data processing unit 11 and

: a main memory 13 runs. An interface unit 19

'known construction is between the input / output module 15 and an input / output gex "ät 17. Man

. recognizes that the interface unit 19 is provided to the form of the data, which of the relevant type of input / Output device 17 recorded or output from this device to bring into the data form as it is on the Main bus (unspecified) and in main memory 13 occur. Depending on the type of input /

'' The output device can therefore use the interface unit 19 analog /

• Digital converter, digital / analog converter and series / parallel

• converter included. It can also be seen that whether the data words on the main bus in series or in parallel

occur, at least each word has a h.1 ressenf eld, a command field and a data field, the relevant fields being marked on the labels on the busbars, for example in the manner of "address bus of the central data processing unit", "command bus of the central data processing unit" or " Data bus of the central data processing unit ^11. It should also be briefly noted that other signals, for example clock pulses and read / write command signals, which are required for the operation of the system, but the description is not necessary for understanding the invention, are not used Finally, it should be noted that, as indicated by the dashed line, a correspondingly allocated or dedicated section of the main memory 13 is used as a random access memory 21 as part of the input / output module 15 and that each different la nd dedicated sections of the main memory; 13 in turn serve for other input / output modules connected to the main bus.

Before referring to FIG. 2 in detail, it should also be said that the components within the input / output module 15 are shown, for example, wired in hardware via switching means. It will be understood, however, that the various components can also be addressable units in order to verify the necessity of using the various switching means
:avoid.

The input / output module 15 thus contains according to FIG a memory 21 random access, which by a corresponding Dedicated or assigned section of the main memory 13 (see FIG. 1) is formed. Addressing the ! Memory 21 of random access is done either from the address bus, not designated, of the central data processing unit or in the manner to be described by one of the four components DMA 23, 25, 27 and 29 for direct

^ eii-j. ι:. ny. These components can be obtained from the company Advanced MicroDevices, Inc., 901 Thompson Place, Sunnyvale, California, under the designation Model AM2940 with "data bus A" or "data bus B" are designated. In order to be able to bring about the processes described above, commands that occur are fed from the central data processing unit and commands from an input / output device to a control logic circuit 31, which in the present case is formed by a conventional logic matrix

that responds to either one or both of the control commands to do the following:

a) Addressing the memory section 21 random access via one of the Circuit elements 23, 25, 27 or 29

or in a yet to be described; Way by the address of the central

: Data processing unit;

b) writing, in a manner to be described, of serial data which either from the input / output device 17 according to FIG. 1 or from the data bus A or from the data bus of the central data processing unit

(see FIG. 1) are derived via the data bus B, at a specific one Address of the random access memory section 21;

c) reading out serial data at a selected address of the memory 21 and such data is ultimately passed on via data bus A or data bus B.

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to the input / output. ^ e advises 17 (Figure 1) or via the data bus of the central data processing unit to the central data processing ; processing unit 11 (see Figure 1)

■ or finally

; d) Forwarding of parallel data from

the data bus of the central data transfer _;

processing unit to the input / output device 17 (see FIG. 1).

In connection with the above statements, it should be noted / that the control logic circuit 31 is designed so that it can respond to the commands from the central data processing unit Gives priority, with the exception of the only case that.

I is just about to conceptualize data from the input / output control device 17 are to be written into the memory section 21, while accessing the memory section 21 through the:

■ Command of the central data processing unit is requested.

In this case, which occurs very rarely, a '< > appears. I.

■ Interruption of the connection to the central data processing \

unit 11 according to Figure 1. ;

From the control logic circuit 31, serial control signals pass to a serial data exchange control device 33 and parallel; Control commands to a parallel data exchange control device 35,

to activate either one or the other device. The serial data exchange control device 33 can be obtained from the company ZILOG Inc., Dell Avenue, Campbell, California, United States of America, under the designation Model Z8530A will. The parallel data exchange control device 35 is made by the previously mentioned company Advanced MicroDevices Inc. under the designation Model AM7303B.

- ■. In FIG. 1, the data bus of the central data processing unit is shown is with one of the central data processing unit associated data buffer 37 (again a device called AM7303B from Advanced Micro-Devices Inc.) / And the address bus of the central data processing unit has a connection with two buffers, which are shown in FIG. 2 in the form of the serial address buffer 39 and the iParallel address buffer 41 are shown. The two

The last-mentioned buffers are from Texas Instruments Inc., Dallas, Texas, United States of America, under the designation Model 54LS244 available. It should be noted that the buffers 39 and 41 are addressable; H. that the to A particular address occurring at a certain time from the central data processing unit determines which of the both buffers is activated.

Between the random access memory section 21, the data buffer 37, the serial data exchange controller 33 and buffers 43a, 43b and switching means 45a, 45b and 47 are connected to the parallel data exchange control device 35. The buffers 43a and 43b are available from Advanced MicroDevices Inc. under the designation Model AM7304B. It should be noted that each of the buffers 43a and 43b is an eight-bit device and that therefore both devices together are sixteen-digit words of the data bus A. The switching means 45a and 45b connect depending on a control signal a from The output of the control logic circuit 31 is either the serial data exchange control device 33 or the parallel data exchange control device 35 with the buffers 43a and 43b. The switching means 47 connect either the buffers as a function of a control signal b from the output of the control logic circuit 31 43a and 43b or the data buffer 37 with the memory section j 21 random access.

To complete the description, it should be noted that the Switching means 49a and 49b and a read / write control device 51 each respond to control signals which are in the

are related to the control circuit 31, in order to control the components 27 and 29 for direct memory addressing when parallel data is passed on to the memory section 21 of random access or obtained from there and to effect the writing in or reading out of data from a selected address (A1, A2, A3 _f A4) of the ¹ memory section 21.

Having described the structure of one embodiment of an input / output assembly, it will be appreciated that the above stated goals can be achieved due to this structure. After the control logic circuit 31 is formed so that the command signals of the central signal processing unit except for the immediate processing of an input / Output command gives priority, the number of interruptions in the operation of the central Signalverarbeitungει unit is reduced to a minimum. Since the memory section in each of the various input / output assemblies is in each case a separate assigned part of the main memory 13 '(see FIG. 1), there is no need for a conflict the interests of the various entry / exit

'. module. The control devices for direct memory addressing

tion only need to address the memory sections 21 and ^! do not have to address the entire memory of the central signal processing unit, which reduces the circuit complexity for the control units.

Within the scope of the invention, the person skilled in the art has a number of possible modifications. For example, if an input / Output module used in a digital computing device in which only serial data are processed, ! so the components which are provided for the treatment of the parallel data in the described embodiment, be omitted. Conversely, in a similar way in a digital computing device, which data can only be parallel processed in the described embodiment for the components provided for serial data processing are omitted will.

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Claims (1)

Claims .1. Digital computing device with direct memory addressing: by peripheral devices, for processing data in ^; serial or parallel form, a central data processing unit (11) being connected to a main memory (13) via a main bus and data in serial or parallel form to this main bus from at least one input / output device (17) via an input / output module (15 ) can be supplied or transferred from the main bus to the input / output device (17), characterized in that to reduce the operational interruptions of the "central signal processing unit (11) due to the operation of the at least one input / output device (17) and the associated input - / output assembly (15) a) a control logic circuit (31) is provided is which on first coded command signals f. the central signal processing unit (11) ^ and responsive to second encoded command signals from the input / output device (17) and a plurality of control command signals corresponding to the shape of those to be transmitted Data and generated according to a certain direction of data transmission, b) that a random access memory (21) is also provided, which is assigned by an associated Part of the main memory (31) is formed, c) that memory addressing means (23, 25, 27, 29) depending on a first group of Control command signals are actuatable to selectively access the memory (21) depending on the address information in the Data words from the central signal processing unit (11) and to be addressed by the input / output device (17) and ^; d) that switching means (4a, 45b, 47, 49a, 49b) respond to a second group of the control command signals and selectively supply data : selected addresses of the random access memory (21) from the central I data processing unit (11) or from ι the input / output device (17) on-I give. j 2. Digital computing device according to claim 1, characterized in that the control logic circuit (31) on the first j group of coded control command signals responds in all cases with the exception of j the case in which data gex-ade over the switching means are transmitted from the input / output device (17) to the / ■ ι random access memory (21). j 3. Digital computing device according to claim 1 or 2, characterized characterized in that the memory addressing means are as follows Building units contain: a) one to the address in each data word from the central data processing unit ; means (11) responsive buffer (39), insofar as this address corresponds to an address in the memory 'random access (21) in order to ' provide a first corresponding address for the ] memory random access (21); b) at least one component (23, 25, 27, 29) 2ut direct memory addressing, which to the address in each data word of - 2 / BATH "ORIGINAL dom input / output device (17) responds, provided that this [ address of an address in the memory ! random access (21) corresponds to: ; at least one second corresponding address for this memory optional Access (21) to provide and c) devices responsive to the first group of control command signals for selective control of the buffer memory and at least one of the components for direct memory addressing. 4. Digital computing device according to any one of claims 1 to 3, characterized in that the switching means are selectively operable such that it from the central Signalverar- * 'data; beitungseinheit (11) to the respective input / output \ apparatus (17 ) pass on. '*