JPS60142756A - Time division multiplex memory bank control system - Google Patents

Abstract

PURPOSE:To attain efficient system processing by recognizing the exclusive state of a memory bus, switching selectively a memory bank during the task processing to a specific memory bank, and allowing the switched memory bank to access other task processing. CONSTITUTION:A memory bank selector 14 is selected depending on the content of output signals 2<0>-2<3> of a decoder circuit 13. The low-order 4-bit and CH of data bus information are stored in a storage circuit C of an I/O port comprising ports 10-12 at the print data transfer task. The CH is stored in a storage circuit B at the data reception task from the high-order machine. Moreover, the CH is stored in a storage circuit A at the task processing not requiring the DMA processing. A DMA control section discriminates the DMA request of each task with priority, makes a DACk signal 5 response to the circuit B and selects the circuits A-C and feeds the result to a selector 14. Thus, the RAM of the required memory bank is accessed to improve the processing efficiency at each task.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention provides a time-division multiplex memory bank control method suitable for time-divisionally controlling memory bank selection [Background of the Invention] For example, in a printer control device, various Multiple memory banks are used for tasks. Conventionally, this type of memory bank control has been based on bank control rather than simply switching multiple memory banks, so program designers must always be aware of the memory bank switching status and perform appropriate operations at any given time. Had to switch to bank. Also, R
DMA (Dir
During a series of memory accesses that depend on hardware such as eotmemory (Acoesa) mode, it is difficult for the program to intervene, so even if the program wants to switch to another bank and access the RAM, it is dependent on the hardware. The program had to wait to switch to another bank until a series of DMA modes were completed, resulting in a drop in overall throughput.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that enables access to memory banks required for various tasks, improves system processing efficiency, and simplifies controlware bank management.

[Summary of the invention]

The present invention allows hardware to freely switch memory banks by passing through gaps in a series of task processes tied to a specific bank, and wait for task processes that require RAM access in another bank. This makes it possible to switch banks without any trouble.

[Embodiments of the invention]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a 16-bit address bus, 2 is an IO/M signal specifying an input/output port, 3 is an 8-bit data bus, 4 is a read/write strobe signal, and 5 is a DMA control section consisting of multiple lines. DACK signal, which is an output signal, 6
is the write enable (WE) which is the input signal of the RAM group.
7 is a row address (RAS) signal, 8 is a column address (ahs) signal, and 9 is an 8-bit RAM address signal obtained by uniquely converting 16-bit address bus information by 14 memory address selectors. 1
0, 11, and 12 are a group of ports consisting of a plurality of ports for holding information on the data bus 3 at the address indicated by the address bus 1, and 16 indicates which DMA channel is permitted to exclusively use the bus from the DMA control unit. 12 by DACK signal 5
This is a decoder circuit for taking out one of the port group outputs and providing it as an input to the 14 memory banks of the next stage circuit.

14 is the output of the decoder circuit 13 and 1 of the address bus 1.
A memory bank selector circuit that takes 6 bits as input and controls a RAM book (bank); 15 is a RAM block group consisting of three 64 x 9 bit RAM blocks; 16 is a RAM block group that controls the contents of the data bus in a write cycle. This is a bidirectional gate group that switches the signal in the direction of writing to the RAM, and also switches the signal in the direction of reading data read from the RAM to the data bus 3 in the read cycle.

Below, the first example is applied to a kanji printer control device.
The operation of the diagram will be explained.

The DMA processing used by the Kanji printer control device includes a data reception task sent from the host machine, and a task to decompose the characters and fonts sent from the host machine into dots so that they can be directly transferred to the printer of the low-order machine. There is an aspect conversion task and a print data transfer TASK that transfers the contents of an image buffer edited by the aspect conversion task to the printer so as to be sent directly to the printer. There are two modes for DM users: cycle steal mode and hiberst mode, but the mode used in the vertical/horizontal conversion task is a series of DMAIA! The number of bytes to be filled is small and the time is short. Therefore, it is a burst mode in which the bus is occupied continuously. Further, the data reception TASK and print data transfer TASK are:
Due to the characteristics of each TASK, the number of DMA processing bytes in a series of DMA processing is large, and the time is also long. Furthermore, for each byte of processing, a temporal space is created due to the relationship between the processing performance of the higher-level machine and the lower-level machine. The cycle steal mode utilizes the above temporal space to process other TASK processes in parallel to shorten the total processing time. Therefore, in the Kanji printer control device, both the DMA processing for the data reception TASK and print data transfer TAI9 are treated as cycle steal mode.

First, the memory layout of the RAM block group in FIG. 1 will be explained. Here, it is assumed that a 16-bit microprocessor is used for the Kanji printer control device. In this case, the address space is OOOOH-FF F
Although only up to 64 bytes of FH can be addressed, there are 1024 m (approximately 74 bytes) of Kanji characters that can be serviced by the Kanji printer controller at any time. For this reason, the memory bank selector 14 shown in FIG. 1 performs bank control to expand the memory space.

Figure 2 (1) shows the output signal 2 of the decoder circuit 13 in Figure 1.
The bank selected by the memory bank selector 14 is shown according to the contents of .about.23.

FIG. 2(2) shows the address space of the memory bank selected in FIG. 2(1). In each bank switching state, the address space from 0OOOH to 7FFFFH is always fixed to the a bank, and this a bank is the program area where the main program is stored and the screen buffer where the code of the character to be printed on the printer is stored. It is an area. The b bank, which is the address space from 8000H to FFFFH, is an image buffer area that stores edited dot image print data to be directly transferred to the printer, and 0 to r or d to f' are data sent from the host machine. 1024 types of Kanji characters are stored.

Naturally, since b-t and d-f are in the same address space, they are used by switching banks. Among these, 0 to r and d-
The banks of f' are physically the same address space.

This bank switching is designed to facilitate the processing of the vertical/horizontal conversion task for Kanji characters.

Since the printer control device is connected to the host machine in exactly the same way as the video data terminal, the host machine writes Kanji characters under exactly the same conditions as the video data terminal (i.e., the address space from 8000H to FFFFH). o', d, θ'.

The memory banks are switched in the order of f', and a kanji character writing service is performed.

Addressing in the above bank switching state is done from the code in the screen buffer area of bank b, where the code of the character to be displayed is stored, like a video data terminal.
Although it is advantageous in a video data terminal that scans and generates character addresses, the above-mentioned c' to (Addressing by /bank is extremely disadvantageous. Therefore, in the printer control device, 01e1
The structure is such that bank control is possible by switching to banks 1ej and f and addressing in the vertical direction to enable reading.

As mentioned above, there are three types of DMA processing tasks for Kanji printers: the data reception task from the host machine, the CG vertical/horizontal conversion task, and the printing task to the printer.
The data reception task and printer print task, which are executed in cycle steal mode, can be processed simultaneously by time-sharing control using the time each task has in the required bank. be.

Next, DMA exclusive use and bank switching operations for each task will be explained.

During the print data transfer task, in order to transfer the contents of the ab bank image buffer to the printer, 10.1 in Figure 1 is performed.
1. I/O boat holding circuit GK consisting of 12
Lower 4 bits of data bus information, OU of OH program
Retained by T command.

Similarly, the holding circuit BKC of the I/O boat is activated so that the ad bank is selected during the task of receiving data from the host machine.
Hold H. Furthermore, P that does not require DMA processing
I O (Program Input 0 output
) rP MA (Program Memory
(Access), the holding circuit A is made to hold OH so as to switch to the ab bank. The DMA control unit prioritizes the DMA requests of each task, responds the DACK signal 5 to the decoder circuit 13, selects one of the holding circuits A to 0, and provides its output as input information to the memory bank selector 14. For example, during the print data transfer task processing time, the DMA control unit responds with the n A c K (ll signal, and the output of the holding circuit C at 12 is given to the memory bank selector 14. Similarly, the The data reception task responds with a DAOK (0) signal and
The output of holding circuit B at 2 is selected. Also, DMA
PIO that does not perform processing.

In the PMA process, since the response signals from the DMA control section are D A c K (0), n A c K (1), the output of the holding circuit A at 121/( is selected, and the input of the memory bank selector 140 The memory bank selector 14 inputs the 16-bit address bus information and the output of each holding circuit, converts the output chip select signal and RAM address signal into unique data, and sends the RA
Performs bank control of the M-block four-bank group 15.

As can be seen from Figure 2+11, during the print data transfer task, the output of the holding circuit G, OH, is the bank selector circuit 14.
and select the ab bank. Similarly, in the task of receiving data from the host machine, the output of holding circuit B is reflected, and the output of holding circuit A is reflected in banks a and o', and in other tasks that do not require DMA processing, the output of holding circuit A is reflected. and select ab puncture.

FIG. 6 is a time chart showing the switching of the operations of the above-mentioned parts. The bus exclusive request by DMA of each task is
gQO~1 is output to the DMA control unit. In DMA control, a priority determination is made, and DA (3KO to 1) is responded to to permit exclusive use of the bus.

The output of the holding circuit A, B, or C, which has been set in advance, becomes the input information of the memory bank selector 14 by the DAOK signal, and the bank is switched. When the dot image buffer edited in bank B of the memory is being transferred to the lower-level printer in the DMA channel mode, a portion of the character is written to bank C' by the terminal controller, the higher-level device. When there is a request for switching, the memory bank selector is efficiently switched by using the bus exclusive permission signal of the DMA control unit and the program by inputting the output signal of the dedicated holding circuit of each channel in advance, and The process of partially rewriting characters to the printer and transferring the image pattern data of bank b to the printer, which is a lower-level machine, are carried out alternately and without waste.

According to this embodiment, since the character rewriting request from the host machine and the print data transfer to the printer are processed in parallel in a time-sharing manner, the total throughput can be dramatically improved.

〔Effect of the invention〕

According to the present invention, in the DMA processing of a plurality of memory banks used in each task, which depends on the hardware, it is possible to freely access the RAM of each memory bank required, so that the processing in each task takes a long time. This has the effect of improving the total throughput because it is processed efficiently without being overloaded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing memory bank switching and memory layout, and FIG. 3 is a timing diagram of bus exclusive use of each DMA and bank switching operation. 1...address bus, 3...data bus, 10...
・Address decoder, 11...synchronization and gate,
12... Holding circuit, 13... Decoder circuit, 14...
...Memory bank selector, 15...RAM7 day 22
Group, 16...Two-way gatero

Claims (1)

[Claims] (1) In a method of controlling multiple memory banks, the exclusive state of the memory bus is recognized, the memory bank is selectively switched in 11 during a series of task processing for a specific memory bank, and the memory bank that has been switched is A time division multiplex memory bank control method characterized in that the memory bank is accessed for processing other tasks.