CA1203644A - Automatically adjustable chip design method - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A method and system for use with high speed automatad electron beam systems in the fabrication of LSI and VLSI circuit chips whereby the dimensions which define the physical sizes of the elements that make up the circuit patterns of the chip can be easily modified to meet the requirements of different wafer processing facilities. A concept of pseudo apertures is employed to define the patterns to be exposed by the electron beam system, even though electron beam systems do not use apertures in the exposing process.
A group of shapes that may be exposed by the electron beam system are defined. These shapes, which function as the pseudo apertures, are then layed out on a grid system, according to established lay out rules, in order to realize a desired circuit pattern. Data specifying the shapes that have been combined to form each pattern are compiled in an aperture table. The data of the aperture table are then used to generate appropriate control signals to cause the electron beam to scan the desired pattern. Changes can readily be made to the data in the aperature tables, as well as the grid system, thereby changing the dimensions and orientation of the circuit patterns as needed.

Description

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AUTOMATICALLY ADJUSTABLE CHIP DESIGN MRTHOD

BACKGROUND OF THE INVENTION

This invention relates to the fabrication of large scale integration tLSI) and very large scale integration (VLSI) circuit ohips, and more particularly to an improved method of using a high-speed automated electron beam system as a tool in the fabrication o~ the chips. Even more particularly, the invention provides a method whereby the dimensions which define the physical si~es o~ the elements that make up the circuit patterns of the chip can be readily changed to meet the requirements of different wa~er processing facilities.
When an integrated c~rouit pattern is fabricated, it is one of many chips, arranged in an orderly array, on a wafer of semiconductor material. Prior to each step in the fabrication process, the wafer is coated with a light sensitive photographic material called a resist. The resist is exposed, by one of a variety of methods, with the circuit pattern corresponding to the next step of the process. After being exposed, the resist is developed. The developing process uncovers those area of the wa~er that are to be subjected to the next step o~ the process and protects those areas of khe wafer that are not to be affected. When the ~abrication process is complete, the wafer is ~cribed along the unused channels between the chips and the individual chips are broken off from the wafer, 36~

The circuit pattern can be exposed on the wafer by a variety of well-known~ prior art methods. ~owever, since the method of exposure is immaterial in terms of the present invention, only the mask method will be discussed.
The circuit pattern for one chip, Por one step of the process, is generated by one o~ the methods described below. A first method employs a ~ask. The mask consists of a multiplicity of chip circuit patterns arranged in the same array as they are to appear on the wafer. The circuit pa~tern, reduced if necessary9 is placed~on a glass plate which is inserted in a stap and repeat camera. The step and repeat camera steps the pattern, reducing it again, if necessary, exposing it after each step on a rPsist coated glass plate in the same array as that of the wafer. The developed glass plate then becomes the maskO
In another method, the stepped and repeated pattern is exposed directly on the resist coated wafer, but again, the actual proc~ss of transferring the circuit pattern to the wafer is immaterial to the present invention.
A different mask is required for each process step in the fabrication of a wafer. Each mask is assigned a layer number. The mask for the fir3t step of the process is called layer-l, the mask for the second step is called layer-2, etc. When smhll scale integration (SSI) and medium scale integration (MSI) chips are fabricated, a common method of making the mask is by the use of "ruby-lith" material. Ihis material consists o~ a sheet of clear plastic, about ten mils thick, wlth a sheet of red plastic, about one mil thick, adhered to it. The outline of every element making up the desired circuit is scribed into the red plastic material uch that it cuts through the red plastic but not the clear plastic~ A
technician then peels off the undesired red plastic r~aterial, leaving the desired circuit pattern. The result, called a "ruby" is typically five hundred times the desired circuit size so photographic methods are used to reduce it to a one-to-one si~e.
The red plastic is transparent to the human eye, to facilitate checking of the rubies, but is opaque to the ligh~ used in photographic reduction process.
As integrated circuit technology has improved to what is called LSI, rubies became obsolete. The sheer volume of the circuits involved made it impractical for a human to peel the unwanted red plastic off without making mistakes. Concurrently, ~he use of computers as a tool in designing integrated circuits became common.
In general 9 a chip consists of circuitry that performs a desired function, and around the periphery of the chip, input buffer circuits and out driver circuits that connect to leads of the chip package~ Typically, the circuitry that performs the desired function consists of a small number of circuit designs, called cells, that are used in large quantities and interconnected in a unique way to perform the desired function. Each cell consists of a ~3~

number of electronic elements, i.e., transistors, diodes and re2istors, arranged in a fixed pattern with respect to each other.
The circuit patterns of the cells, and the other circuits on the chip, are different for each step in the processing of a wafer, requiring a different mask for each step.
The computer, because of its high speed and large storage capacity, is an ideal tool to use in designing LSI and VLSI
circuits. The data describing the circuitry of each cell, as well as the input buffer and output driver, for each step of the wafer process is stored in the computer. This data typically comprises the dimensions o~ the rectangles that make up the circuit and the dimensions of the spacings between the rectangles. A chip designer, using appropriate programs, can place the cells, input buffers and output drivers, as desired, within the boundary of the chip. Other programs are then used to interconnect the circuitry to perform the desired function. The computer programs process this data as the chip design evolves and build a data base corresponding to each process step, or layer, of the wafer. When the chip design is complete, the data base for each layer is used to generate the mask for that layer.
In addition to the ruby9 another tool used to generate masks in the prior art has been the photo-plotter. A photo~plotter consists, basically, of an X-Y table, a light source and a set of apertureq.
A piece of photographic film is placed on the X-Y table and held flat and in place wlth a vacuum system. An aperture, i.e~ 9 an ~2~3~

opening of the desired shape and size, is positioned between the light source and the f~ilm. The X~Y table then ~oves the film under the light source to expose the desired pattern. The light source can be turned off while the table is being moved without an exposure or while an aperture is being changed, turn on while the table is being moved to expose a line or shape, or turned off whlle the table is being moved to a ne~ location and then ~lashed momentarily ~o e~pose the shape oP the selected aperture. The position of the X-Y
table, the aperture selected and the light source are all controlled by the data ~rom the computer. In this fashion, the data is used to generate the circuit pattern for one layer. The pattern generated with the photo plotter is usually several hundred times normal size and photographic reduetion methods are used to reduce it to the necessary one-to-one size. The photo-plotter is, of course, much more accurate than the manual "ruby" method, and has essentially replaced the "ruby" method for all but the simplist of SSI or MSI
circuits~
As integrated circuit technology continued to progress to what is now called VLSI, the photo-plotter method has essentially been replaced with an electron beam system. There are two basic reasons for this. One is that in VLSI t~chnology the dimensions used are on the order of a micron. This is approaching the wavelength of light and therefore light cannot be used to make the exposureO The second reason, and every bit as important, is that the photo-plotter method ~ ~ A ,~ql takes too much time to make the masks Every exposure made with ~
photo-plotter involves a movement of the X-Y table. The amount of circuitry in a VLSI chip is so large that the time required to expose a layer with a photo-plotter could exceed the mean time between failure (MTBF) of the photo-plotter. In contrast, the electron beam of an electron beam system is deflected electro-magnetically and takes a very small fraction of the time required for an equivalent movement of a photo-plotter.

The principles involved in making a mask are the same whether a photo-plotter or an electron beam system is used. In the electron beam system, photographic film is replaced by an emulsion coated glass plate, the light source is replaced by the electron beam~ and there is physically no aperture.
A wafer processing facility is usually called a "wafer line".
Each wafer line has a set o:E requirements that must be met when the wafers are processed or the final product may not function as designed.
Among these requirements are that the dimensions used on the various circuit patterns of the masks used in the fabrication steps be tightly controlled. Because a manufacturer of VLSI chips will typically attempt to find a second or third source for the chips, either from other wafer lines within the same company or from other companies, and because each "wafer line" has its own unique set of requirements, including dimensional requirements, which ~2~:)36~

requirements require a unique but functionally equivalent mask for each line, it would be an advancement in the art ko provide a convenient way to generate these different, but equivalent masks.
Heretofore, a human has had to go through all the programs and data involved in a chip design and change all the affected dimensions.
This is not only is time con3uming, but virtually guarantees that mistakes will be made. ThPse mistakes may not only cause catastrophic failures (which are usually easy but expensive to solve), but they may also cause a degradation in circuit performance (which i~ a diPficult problem to solve).

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SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of readily making different sets of masks for the same wa~er, the mask sets being functionally identical7 but having the d1mensional changes in the circuit patterns necessary to meet the requirementq oP the particular wafer lines in which the mask sets will be used.
It is a further object of the present invention to provide a system of defining the masks or patterns that are to be exposed on a wafer in such a way that desired modifications, including scaling, can easily be realizedO
The above and other objects of the inve~tion are realized by utilizing a concept o~ easily visualized and understood pseudo apertures from which control signals that ultimately define the movement of the electron beam system can be generated, even though the masks or patterns are exposed on the electron beam system without the use of actual apertures. Advantageously, the invention employs several program statements that allow the aperture to be easily defined, and that further allow other necessary dimensional parameters to be readily varied.
As indicated previously, apertures are used on photo-plotters to shape the light beam into the desired shape to expose the film.
In contrast, an electron beam system exposes a shape by deflecting the electron beam over the entire area of` the desired shape. The present invention allows a designer to design a chip as if apertures of the specified size and shape were to be used to form the exposure 6~

on the electron beam system. The necessary conversion from the pseudo apertures to the movements which wi.ll deflect the electron beam may advanta~eously be performed by a computer.
The aperture concept of the present invention allows the user not only the ability to perform chip design using the easy-to-visualize aperture, but also allows the user to readily make ~imensional changes, which dimensional changes are required if the masks are to be used on wafer lines having different layout rules from those of the wafer line for which the mask was originally made.
lQ Program statements for use by computer are provided by the invention which allow new masks to be made with dimensional changes, as required for different wafer processing lines, by changing a few parameters in the statements. As an example, the electron beam diameter, the increment of movement of the electron beam, the scaling factor or the units used in the program, and the user defined grid on which the circuit elements are to be placed, can all be varied by changing parameters in a few statements. New masks can then be made and used on the particular wafer line that necessitated the change.
To summarize, according to a first broad aspect of the present invention, there is provided in an electron beam exposure system that includes means for selectively scanning an electron beam on an object in order to expose a desired pa~tern thereon, a method for defining the particular pattern that is to be exposed _g_ by the scanning electron beam on the object, said method comprising the steps o~:
(a) defining a set of shapes that may be scanned by the electron beam;
(b) specifyi.ng each of said shapes with aperture data that de~ines the particlllar type of shape, such as line, rectangle, or square, and the relative size of the shape;
(c) defining a grid system having unit dimensions;
(d) selectively positioning a group of said shapes on said grid system so that a desired pattern is realized;
(e) generating an aperture table tha~ contains a collection of aperture data corresponding to the group of shapes placed on the grid in step ~d); and (f) usi.ng the collection of aperture data from step (e) ~o control the scanning of said electron beam so that the desired pattern is exposed on said object.
According to a second broad aspect of the present invention, there is provided a system Eor defining the patterns to be exposed on an integrated circuit chip by an electron beam system, said electron beam system including means for selectively scanning the integrated circuit chip with an exposing electron beam in response to control signals, said pattern defining system comprisin~:
means for defining a set of shapes that may be scanned by -9a-~t3~

aid electron beam;
means for specifying the location on the chip where a particular shape defined by said defi.ning means is to be scanned;
means for combining a plurality of said shapes at specified locations to define a desired pattern; and means for converting the defined pattern to appropriate control signals that cause the electron beam system to expose the desired pattern on the integrated circuit chip.

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BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features, and advantages of the present invention will be more apparent Prom the following detailed description of the preferred embodiment~ presented in conjunction with the following drawings, wherein:
FIGURES la, lb, lc, ld, le, and lf show typical mask patterns that may be used for the first six layers of a basic block of a chip;
FIGURE 2 shows the basic block formed by the mask o~ the first six layers of the grids on which the circuit elements are placed;
FIGURE 3 shows three ba~ic blocks that have been interconnected by a Yirst metalization layer to form three representative cells;
FIGURE 4 dep.icts how one of the grids used in the design of the chip is determined;
FIGURE 5 shows how a se~ond grid used in the design of the chip is determined;
FIGURES 6a, 6b~ and 6c illustrate three dif~erent methods that can be used to specify a rectangle;
FIGURE 7 is a flow chart showing how the library functions of the present invention are loaded into a computer memory device;
FI&URE 8 is a flow chart showing the library functions of the present inventlon for a single layer are executed;
FIGURE 9 is a flow chart showing the execution detail of a library function;
FIGURE 10 is a flow chart showing how the data record ll describing a rectangle is generated by the present invention; and FIGURE 11 shows the locatlon oP the rectangle of FIGURE 10 and the various dimensions deri~ed.

~2~3G44 DESCRIPTION OF TE[E PREFERRED EMBODIMENT
The following is a description of the best presently contemplated mode of carrying out the invention. The description is given only for the purpose of illustratiny the general princi-ples involved in the invention and should not be taken in a limit-lng sense. The true scope of the invention can be determined by referring to the appended claims.
FIGURE 1 shows a mask pattern that may be used for one basic circuit block of a CMOS chip for layers one through six.
Although the chip contains other circuits besides the basic block, only the basic block is discussed in the following description, since it is sufficient to illustrate the principles of the inven-tion. The same principles apply to all layers and all circuits on the chip. Also, the invention is not restricted to CMOS tech-nology but can be used with any integrated circuit technology.
FIGURE la shows a field mask used for ]ayer~l. During the first step of the fabxication process, the areas within the eight rectangles, 10-24, are protected by resist and the area outside the ~3~

rectangles is subjected to the chip fabrication process~
FIGURE lb shows mask used on layer-2 to form a p-well. This layer-2 mask, the cro~s-hatched rectangle 26, is superimposed on the layer-l mask to show its relationship to the basic block. During the second step of the fabrication process, the area outside the cross-hatched recta~gle 2b is protecte~ by resist and the area inside the cross hatched rectangle is subjected to the chip fabrication processO
FIGURE lc shows the poly gate mask used on layer-l. This layer-3 mask, comprising the four cross-hatched lines, 28-34, with a square at each end, 36-50, is shown superimposed on the layer-l mask in the figure to show its relationship to the basic block. During the third step o~ the fabrication process, the cross-hatched areas of the mask, 28-50, are exposed to the chip fabrication process, while all other area3 are pro~ected by resist~
FIGURE ld shows the P+ implant mask used on layer-4. This layer 4 mask, which includes the three cross-hatched rectangles, 52-56, is shown superimposed on the layer-l mask to show relationshlp it has with the basic block. During~the fourth step of the fabrication process, the areas within the three cross-hatched rectangles 52-56, are protected by resist and the remaining area is subjected to the chip fabrication process.
FIGURE le depicts the NI implant mask used on layer-5. This layer-5 mask, compri3ing the three cross-hatched rectangles, 58-62, 73~

is likewi~e superimposed on the layer~l mask to show its relationship to the basic block. During the fifth step o~ the chip fabrication process, the areas within the three cross-hatched rectangles, 58 62, are protected by the resist and the remaining area is subjected to the process.
FIGURE lf sbow the contact mask used on layer-6. Thi~ layer-6 mask~ which includes the thirty six small squares 74, is shown superimposed on the layer-l mask in the ~igure to show its relationship to the basic block. During the sixth step of the process, the area outside the thirty six squares 74 is protected by the resist, and the area within the small squares 74 is subjected to the process.
The first six process steps described above are used to form the basic circuit block. Each block, for the example under consideration, consists of eigh$ transistors.
Re~erring ~o FIGURE la, after the fi~th process step the areas within the rectangles 18 and 20 each contain two N-channel transistors while the areas within the rectangles 22 and 24 each contain two P-channel transistors. The eight transistors are arranged in complimentary pairs with a common gate, each pair consisting of an N-channel and a P-channel transistor. The four poly strips, 28-3ll of FIG~RE lc, form the common gate for each pair. The contacts oP Figure lf provide an opening, through an in.sulating layer of glass, to allow the circuit elements to be interconnectedO

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The basic circuit block perform~ no logic ~unction since the eight transistors are not connected to a volta~e source or ground and are not interconnected. Four more process steps are required to convert the blocks into cells and interconnect the cells (as well as the other circuits on the chip). These steps include: layer 7, the contactq made in layer 6 are interconnected in a desired manner with metal lines by depositing a first layer of metalization; layer 8, a layer of insulating glass i3 deposited and vias are etched in it t~
expose the contacts to be used in ~he next step; layer 9, the exposed contacts are interconnected in the~desired manner with metal lines by depositing a second layer o~ metalization, completing tha electrical interconnections of the chip; layer 10, a protective layer of glass is deposited over all of the chip except the bonding pads whioh will be used to connect the input/output circuits of the chip to chip package leads. Steps seven, eight and nine "personalize" the chip, i.e., interconnect it to perform a particular function.
TABLE 1, below, shows a typical set of layout rules for the first seven layers of the preferred embodiment~ A set of rules exist for the last three layers but the first seven are sufficient to illustrate the present invention. The rules are established by a particular wafer processing line~ The minimum dimensions shown reflect the capabilities of tbe processing line, i.e., if a chip design violates the rules, then it is unlikely that the waf`er can be processed ~hrough all the steps without introducing de~ects which will cause catastrophic failures within the circuits of the chip.
The minimum layout rules of Table 1 are determined by the equipment, chemicals and materials used in the wafer line along with the experience of the people working on the llne~ Each wafer line has its own set of layout rules. In some cases, especially i~ the lines are in different companies, the rules vary so much that masks used on one line can not be used on the other line.
Examples of the ruleQ are: rule 1.2 states that the space between rectangles 18 and 20 and between rectangle~ 22 and 24 of FIGURE la can not be smaller than 5 microns; rule 1.3 states that the spacing between rectangles 18 and 22 and between rectangles 20 and 24 of FIGURE la can not be smaller than 5 microns; rule 3.2 ~tates that the gap, or space, between all the rectangles 28-50 of FIGURE lc must be at ]east 3 microns; rule 5.2 states that space between the rectangles 58-62 and 18 20 oP FIGURE le must be at least

2.5 microns.
All the rules shown help determine the sizes of the rectanglas used in the six masks of FIGURE 1 and their relative location within the basic circuit block. As stated previously, the minimum layout rules reflect the capabilities of the wafer lineO They are not established because of circuit parameters, That is, if a chlp were designed using all the minimum dimensions o~ TABLE 1, it could be fabricated by the wafer line with reasonable yield.

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TABLE 1.
,__ __ CMOSl LAYOUT ~ULES

All dimension~ in microns Min. Rule 1. Field Mask (clear field) layer = 010 1.1 Source Drain width 5.0 1.2 P+ to P+ and N-~ to N+ dif~usion spacing 5,0 1.3 Spacing bet~een N~ and P~ regionq in the 5.0 same substrate 20 P-Well Mask (dark field) layer = 020 201 Overlap of P- over N~ drain 3.5 2.2 Spacing between P- opening to P-~ drain 7.0 2.3 Spacing between P- opening and N+ contact 5.0 di~fuslon into N substrate 3. Poly Gate Mask (clear field) layer = 030 3~1 Minimum gate length 3.0 3.2 Poly to poly spacing 300 ~2~3~

3.3 Gate overlap onto field oxide 3.0 3.4 Overlap around poly contact 3.0

4. P+ Implant Mask (clear field) layer - 040 4.i Overlap around ~ areas 2.5 4.2 Spacing from mask edge to P+ doped areas 2.5

5. N+ Implant Mask (clear field) layer = 050 5.1 Overlap around P+ areas 2.5 5.2 Spacing from mask edge to N~ doped areas 2.5

6. Contact mask (dark field) layer = 060 6.1 Minimum poly contact size 205 6.2 Minimum diffussion contact size 3.0 6.3 Spacing of SD contact to edge of field mask 2.0 6.4 Spacing between edge of diffusion contact 300 to poly gate

7. Fir~t Metal Mask (clear field) layer - 070 7.1 Minimum line width 4.0 7.2 Minimum spacing lOum length 3~0 7.3 Minimum spacing lOum length 3.0 7.4 Minimum overlap around contact 2~5 7.5 Mlnimum overlap around via 2.5 3~

Continuing with a description of the representative chip design of FIGURES la-lf, FIGURE 2 shows a basic circuit block ~ormed by the masks of the first six layers~ The rectangles that make up the block are positioned on elther nine micron grid 70 or a ix micron grid 72. The contacts formed by layer 6, to which the metalization layers will connect when interconnecting the transistors of the block to ~orm a cell and when inkerconnecting cPlls, are the small squares 740 The figure shows both the ground and VDD bus at the bottom of the block9 although th0se buses may be located at any convenient locatlon. In the preferred embodiment, the ground and VDD bus are alternately used between blocks.
FIGURE 3 shows three blocks that have been interconnected ("personalized") by the first metalization layer, layer-7, to ~orm three different cells. The logic diagram and schematic diagram for each resulting cell are also included in the figure. The interconnecting metal wires and the contacts to which they connect are shown cross-hatched in the figureO The AND-OR-INVERT gate formed in the top block uses all eight transistors o~ the block while the 2-input NOR gate and 2-input NAND gate formed in the middle and owner block~, respectively; only use four transistorq each. The remaining four transistors iTl each of the middle and lower blocks could be used to ~orm another cell, i~ desired.
With the preceding as background, the process of designing a 3~4-~

CMOS VLSI chip can now be explained. The first step is to design the electrical circuits that will be used on the chip, including their position on the chip, and the masks o~ the first six process steps that will be used to fabricate them. The ma~ks have to meet the requirements of the layout rules for the particular wafer line ~hat is to be used~ Representative rules are ~hown in TABLE 1, After the first step of the design has been completed as described above, the second step is the design of the cells. The cells consist of interconnected transistors of the block, as described above. A cell is not limited to one block and may consi.st of as many blocks as necessary to perform the desired logic function.
A cell that performs a particular function is only designed once. That is, all functionally identical cells will be interconnected identically. For example, all two~input NAND gates used in the preferred embodiment will be interconnected as shown in the bottom cell of FIGURE 3. This is done so that all functionally identical cells will have similar electrical characteristîcs, since the manner in which the cells are interconnected helps determine their electrical characteristics, such as delay time, rise and fall time, etcO
The third step in the design of the chip i5 the selection of the cells that will be used, the assignment of input and output pins, and the interconnçction o~ all the cells and input and output buffers to perform the desired logic functionO The result of this 3~

third step is the ~asks that are u~ed during the last four process steps to personalize the master slice. Again, the masks must meet the requirements of the appropriate layout rules.
Computers are used extensively in the design of VLSI chips.
The sheer volume of the data involved dictates that the task can not be performed manually. For example, in one embodiment, a CMOS
master slice contains 2250-blocks, or 18,000~transistors~ (A
"master slice" is a wafer having a large number of identioal blocks formed thereon by the process of the first six steps. These blocks, are then interconnected or "personalized" by the process o~ the last ~our steps (7-10) de~cribed above. While the present invention does not require that the master slice concept be used, its utili~ation does simplify the application of the invention.) Typically, special purpose programs are written to simplify the design task. The da~a specifying the first six layers of the master slice and the data specifying the interconnections that ~orm the cells, are stored by the computer program, typically on a rotatîng disk storage systemO The data is stored by layer number, such that the data for any layer can be changed or processed without affecting the other layers.
A logic designer can use the design-oriented computer programs to interconnect the cells without any concern as to how the master slice is formed or how the blocka are interconnected to form individual cells~ Programs are used which route the interconnecting 12~

traces between the cells used in the design and the other circuits of the chip. The~e programs com~ine the data that describes the fixed interconnections, i.e., the calls used and other circuits of the chip, with the interconnections of the logic design. This combined data is partitioned inko layers 9 by the program~ and stored. The program can then process the data describi~g~.5any of the ten layers involved in the embodiment and generate an output which is u~ed to control an electron beam exposure sys ~m. The electron bea~ system exposes the circuit pattern on a resist coated glass plate to generate the mask.
The masks generated using the process described above will meet the layout rules of the wafer line on which they are intended to be u ed, but may be unsuitable for use on any other waf`er line because of the different layout rules. In order to use the mask set on another wafer line, it is necessary to change all the dimensions ~hich violate the layout rules (it is assumed in this description that the dimensions can be changed without affecting the functionability o~ the circuits)O In some cases, this can be a formidable task. For example, it is not uncommon for as many as 150-cells to be defined for use on chip designs. Each cell uses several wiring traces to interconnect the transistors of the block.
Thus, if the wiring traces have to be made wider to meet the new layout rules of a different wafer line 9 the data describing the line width in each o~ the 150-cell descriptions would have to be found .~

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and changed, along with the data describing the line width of the wiring traceq of the other circuits ~n ~he chip and the interconnecting traces that personalize the chips.
The present in~ention uses several special program statements and the concept of p~eudo apertures to provide a me~hod for easily changing dimenslons to meet the requirements of different layout rules. As explained 9 an ap~rture is used on photo-plotters to form the beam of light into the desired shape, e.g~, circle, rectangle, square, etc. The electron beam, on the other hand, does not US8 an aperture. Rather, a shape is exposed by causing the electron beam to deflect over all the area of the shape.
The program o~ the present invention is written as if apertures are used by the electron beam system. The designer can then use the more easily visualized and understood concept of apertures in the chip design. BePore the aperture data is used by the electron beam system7 the program converts this aperture data into the appropriate electron beam commands.
The pre~ent invention uses the concept of an aperture table with a plurality of position~ in the table. Each position can be de~ined to hold the definition of an aperture. An aperture table can be defined for each mask layer. In a preferred embodiment;
twenty-four position~ are included in the aperture table. Thus7 as many as twenty four different apertures can be used for each mask layer O

~1 O~f ~ A

The aperture table is defined with a program staSement which has the format:
AT K NPOS NAPT NPOS NAPT NPOS NAPT
The letters AT are a mnemonic for "Aperture Table". K is used as a flag. If K~l, the statement will clear the aperture table of all previously defined apertures before using the remaining parameters to de~ine new apertures for the positions chosen, as explained below. If K=O, the existing aperture table is no~ cleared and the remaining parameters are used to define apertures for the positions chosen, as e~plained below. If K=-19 only the next parameter, the fir~t NPOS, i3 used. The value used for the first NPOS is a scaling factor for negative aperture values.
The parameter NPOS de~ines the aperture table position ?
through 24, which will have the aperture size specified by the following NAPT "loaded" into it~ The posi~ions specified do not have to be in numeric order and up to eight AT statements can be used to load any positions in the aperture table;
The parameter NAPT defines the aperture in user defined units.
If the aperture is specified as a negative number, it will be divided by the scaling factor (defined when K=-l, as explained above) before being used. NAPT can have the following forms:
1000+N - This defines a line with short ends and a width of N
user defined units.
2000+N - Thl3 de~ine~ a line with long ends and a width of N
user defined units.

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3000~N - This de~ines a square of NxN us~r defined units~
lXXYY - This defines a rectangle of XX by YY user defined units.
2WWLL - This defines a notched pad consisting of t~o rectangles with a width WW and length LL exposed with their centers in the same place but with one rectangle rotated 90-degrees.
When a line is exposed by the electron beam system from point A
to point B, it extends beyond the points A and B by some amount D If a 2000+N aperture is used (long ends), the line length is A-~N.
ThaS is, the line extends 1/2 the line width, N, at each end of the line. If a lOOO~N aperture is used (short ends~, the line length is A-B~N-2~ That is, the line extends 1/2 the line width, N, minus one user defined unit, at each end of the line. This to eliminate a double exposure, and the "ballooning" of the exposure that results, at the corners were two lines meet at a right angle.
An aperture, defined in the aperture table, is used by a statement which has the Pollowing form:
AP NPOS
The letters AP are a mnemonic for aperture. The parameter NPOS
specifies a position, 1 through 24t in the aperture table. when the AP statement is used, all subsequent exposures will be made using the aperture from the table position specified, until another AP
statement is used to change the definition.
TABLE 2 shows a typical aperture table used in the preferred embodiment. The aperture table positi3n number t and the use of the ~6 ~ ~ ~ 3 ~ ~ ~

aperture, are limited ver~ically on the left side o~ the Table. The layer number, defined by a three diglt mlmber, 010=layer-1, 020=layer-2, ekc., are listed horizontally across the table.
TABLE 2 lists all the apertures that are de~ined. For example, aperture position-l is used to draw a line with short ends and is only used on layers 3, 7 and 9. When used on layer 3, it has a width of 3-units while on layers 7 and 9 it has a width o~ 4-units.
Aperture position-l is-not defined for any other layers~

APERTUR~ T'bL_ D~F~N ~iDN

APT LA = 010 020 030 0l10 050 060 070 080 090 100 1 Line ' ' 1003 ' ' 1004 ' lOol 2 Poly Cont ' 3008 ' ' -3005 3008 ~
3 S-D Cont ' ' ' ' 333008 9 ~ ~
4 VIA ' - 73008 -3005 3008 5 Field 1007 3015 ' 3012 3012 6 Power VIA ' ' ' ' ' ' ' -11005 11108 7 Horiz Bus ' ' ' ' ' ' ' ' 1008 9 IODR 10607 ' ' ' ' 1010 -11005 10 IODR Lines ' ' 1005 ' ' ' 2008 ' 2008 12 Diag Poly C ' 3008 ' ' -3005 20806 ~3~

13 Diag SD C ' ' ~ ' ' 3003 20806 t ~ ~
14 Diag Via 7 ' ' ' I '20806 -3005 20806 ' 16 SR Power ' ' ' ' ' '3012 3004 3012' 19 Test Pads ' ' ' ' ' '3072 3068 3076 3072 20 DC4 Pads ' ' ' ' ' ' '' 3010 3002 21 N-ch Poly ' ' 1003 22 P-ch Poly ~ ' 1003 24 I/O ' ' ' ' ' ' 30963090 3100 3092 TABLE 3 shows that portion of the computer program which defines the aperture table for each layer. The BR statemen~ used in the figure has the following format:
BR STNO LA LA LA LA LA LA
This statement causes the program to branch over (skip) the number of following statement defined by the parameter STNO if the layer number is not equal to any of the six numbers qefined by the 9iX LA parameters. Only one layer number has to be defined.

__ APERTURF. TABLE PROG~AM

AT -1 2 Set scale for neg. APT

-~D3~

BR 1 020 P-Well BR 4 070 ALl AT O 163012 lg3072 243096 AT 1 4-3005 6~11005 9-11005 ~36~

AT 0 7 1008 10 2008 14 20~06 As mentioned previously~ the design data describing a chip design is partitioned by layer numberO When this data is to be processed in preparation for making masks on the electron beam system, the layer number is speci~ied to the program as part of the input data.
The program of TABLE 3 i~ similar to a sub-routine. At some point in the main line program, a D0 statement causes the execution of the ~irst AT statement of TABLE 3. The BR statements are executed until a match is found between the specified layer number and the layer number of the BR statement. when thi~ occurs the AT
statements following the BR statement are executed, establishing the aperture table for the subsequent data to be processedO The remaining BR statement, if any, are executed and eXecution returns to the main line program~

3o 36~

The aperture concept of the present invention, in conjunction with the program of TA~LE 3, greatly simplify the changing of dimensions. If, as in the example given previously, it is necessary to change the width of the metalization traces that interconnect all the circuits of the chip, it is only necessary to change the AT
statement~ that define aperture~l for layers 7 and 9? and use the program to reprocess the data and generate new mask~ on the electron beam system.
Two additional program statements form part of the invention.
They are the dimension (DI 3) statement and the origin (OR 3) statement9 shown in TA~LE 4. The DI 3 statement has the following format:

This dimension statement is used to set the dimensions used by the electron beam systemO The letters DI are a mnemonic for DIMENSION
and the first parameter, 3, identifies the type of dimension statement. The parameter FLD specifie~ the Sield size (the area over which the electron beam can be deflected). When all o~ the circuit patterns within one field are exposed, the mask is moved to align another field under the electron beam~

3~

TABLE_ DIMLNSION AND ORIGIN STATEMENTE

OR 3 Sl S2 COL ROW LVL L

The dimensions used by the electron beam system are controlled by digital to analog converters (DACs). The numbçr of least signi~icant bits o~ the particular DAC used for one unit of dimension determines the unit size. For example, if only the least significant bit (LSB) is required for one unit of movement, the unit size would be one-eighth that of the unit that uses three,least significant bits for one unit of movementO Advantageously, movements within the electron beam system may be measured within a grid system having an origin. The last three parameters of the dimension statement define these dimension units as follows:
LSBO is the number of DAC LSBs ~or one unit of origin movement;
~ LSBL is the number of DhC LSBs for one unit of lçngth movement; and INC i~ the number of DAC LSBs for one qpot incremen~.

~2g~3~6~

The OR 3 statement has the following format:
OR 3 Sl S2 COL ROW LVL L
The letter OR is a mnemonic for ORIGIN, and the first parameter, 3, identifies the type of origin statement. The paramet rs Sl and S2 define the number of spots per user defined unit, the spot being defined as the diameter of the electron beam used to expose the mask.
The parameters COL and ROW define the number of user units that are used for the user defined horizontal and vertical grid. FIGURE
2 illustrates how this grid is used. The elements that make up the basic circuit block are placed on grid points rather than absolute dimensions. The remaining parameters, LVL and L, relate to origin levels, and are of no interest to the present invention.
The use of the dimension and origin statements of the present invention can be illustrated by returning to the example o~ the line width change. In a preferred embodiment, the field size is normally 512-microns, the spot used is normally one-half micron, and the user unit used in the program is normally one micron. The physical slze of the spot is selected by a switch on the control panel of the electron beam system. However, an exposure is made by moving the electron beam in one spot increments and since the program generates the data to control the electron beam, the spot size must be known to the programO

3~

The program statements of the invention for the line exposure example would be:

The DI statement defines the field to be 512-microns square. The DACs are twelve bits wide, which means a number of up to 4096 could be defined. Since the field is defined to be 512 microns, the least significant bit of the DACs has a value of 1/8 micronO (512 is 1/8 of 11096). Beaause the spot is lJ2 micron, the last three parameters of the dimension statement, defining the unit of movem0nts, are set at 4, i.e., 4 x (l/o micron) = 1/2 micronO

~2~36~

The OR statement ~efines the scale factor Sl/S2 to be 2/1 = 2.
That is, two spots are equal to the user defined unit of one micron used in the program. Also defined in this statement is the horizontal and vertical grid size for the user defined grid (FIGURE
2). This grid size is defined to be 9 user units.
The AT statements define aperture number 1 to be 4 microns.
Thus, when the data is processed and the mask is exposed on the electron beam syskem, the lines will be exposed by eight sweeps of the electron beam, each sweep one spot away from the previous sweep (8 sweeps x 1/2 micron dia. = 4 micron width).
Now, suppose the wafer is to be fabricated on a wafer line which requires the line width to be a minimum of 4.75 microns. One solution might be to change the AT statements to and remaking the masks for layers 7 and 9. These masks would meet the minimum line width requirament of the waPer line since the lines would be 5 microns wide. Suppose it is necessary ~o use a line width of 4.75 microns because a 5 micron line width would cause the space between the lines to be so small as to violate another layout rule. The program statements of the invention would be changed to:

~33~

AT 1 1~1019 AT 1 1-1019 ~

A line width of 4 n 75-miorons can not be exposed with a 1/2 micron spot so tha spot size will have to be changed to 1/4-micron. The DI statement still defines the field to be 512-microns (it could be defined as 256-microns, giving the least significant bit of the DACs a value of 1/16 micront if more accuracy is required). Therefore, the least significant bits o~ the DACs are still l/8-micron so the last three parameters 9 defining the units of movement, are set at 2, i.e., (2xl/8 micron - 1/4 micron3.
The OR statement defines the scale ~actor Sl/S2 to be 4il = 4.
That is, four spots are equal to the unit, i.e.1 one micront of the user unit used in the program.
The "AT -1 4" statement ~tates that any negative aperture used is to have it5 stated value divided by ~our before use~ The ~2V3~

remaining two AT statements define the aperture f~r the line to be -19 mlcrons. Thus, when the data is procecsed and the mask exposed on the electron beam system, the lines will be exposed by nineteen sweeps of the electron beam, each sweep one spot away from the previous sweep (19 sweeps x 1/4 micron dia.=4.75 micron width).
FIGUR~ 2 shows khe rectangles of the basic block being positioned on either six micron grid or a nine micron grid. The grid used is established by the COL and ROW parameters of the OR 3 statement of TABLE 4. The actual values used are established by the layout rules, as explained in the~following paragraphs.
The six micron grid is determined by the spacing between the poly gate Qf layer-3 and the contacts of layer-6, as illustrated in FIGURE 4. The contact 74 is shown centered between the poly gates 28 and 30. The wiring rules of TABLE 1 establish the minimum size of the dimensions a, b, c, in the following manner.
Rule 3.1 states that the minimum gate length ~width, as shown in the figure) is 3.0 microns. Thus, a = 3.0/2 = 105 microns.
Rule 6.4 states that the minimum spacing of a contact to a poly gate is 3.0 microns. Thus, b = 3.0 microns.
Rule 6.2 states that the minimum contact size is 3.0 micronsO
Thus, c = 3 n 0/2 = 1.5 microns.
The sum Or a, b and c i9 600 microns, which is one of the grids used in the above examples Or the preferred embodiment. The nine micron grid is established by the spacing between the metal traces -~2~36i~L~

and the metal pad at the end of an adjacent trace, as illustrated in FIGURE 5. The trace 82 is shown a distance f away from the pad 80 at the end of an adjacent trace. The pad 80 iA centered on the contact 74. The minimum ~ize of ~he dimensions d, e, f, and g is cstablished by the wiring rules of TABLE 1 in the following manner:
Rule 6.2 states that the minimum contact size is 3.0 microns.
Thus, d = 3.0/2 = 1O5 microns.
Rule 7.4 states that the minimum overlap around a contact is 2.5 microns. Thus, e = 2.5 microns.
Rule 7.2 states that the minimum spacing between metalization over a length less than 10-microns, i.e~, when a metal trace is next to a metal pad, is 3.0 microns. Thus, f = 3.0 mîcrons.
Rule 7.1 states that the minimum width of a metal line is 4.0 microns. Thus, g - 4.0/2 = 2.0 microns.
The sum of d, e, f, and g is 9.0 microns. This is a minimum value and a grid oP 9.0 microns is used in tha examples of the preferred embodiment. The sum of 2d plus 2e, 8.0 microns, also establishes the size of aperture number three on layer-7.
FIGURE 6 shows the ways in which a rectangle can be described to the program of the present invention ~there are additional ways, but the three shown are sufficient to illustrate the invention).
The three ways are by specifying one point and an aperture (FIGURE
6a); by specifying two points and an aperture (FIGURE 6b); and by spec~fying four points and an aperture (FIGURE 6c).

~ ~9 IIL~V~ ,~

The rectangle of FIGURE 6a is described by specifying a point 84 and an aperture size. The aperture would be speci~ied as a 3000-~N size, as e~plained in the description of the AT stat~ment.
The ~ollowing program statement would cause the rectangle to be exposed by the electron beam system:
MA -3 Xl Yl The mnemonic MA means move absolute to the coordinates Xl,Yl 86, i.e., the coordinates are with respect to the origin and not with respect to the previous location. The parameter 3 means "flash" or expose the current aperture when the speciried position i5 reached, and the minus sign means that the coordinates Xl,Yl are in grid units.
FIGURE 6b shows a rectangle 92 that is described by two points 88 and 90 and an aperture si~e. The aperture would be specified as a lOOO~N size, as explained in the description of the AT statement.
The ~ollowing program statement would cause the rectangle to be exposed by the electron beam system:
MA -4 Xl Yl X2 Y2 This is a move absolute statement, as described previously. The initial move is to the point Xl,Yl 88. The parameter 4 means thak a rectangle is to be drawn between the starting point Xl, Yl 88 and X29Y2 90. The size (height) f the rectangle is determined by the aperture selected. The negative sign means that the coordinates Xl,Yl and X2,Y2 are in grid units.

36~

FIGURE 6c shows a rectangle 9l~ that is specified by four points 96-100 and the aperture size. The aperture would be specified as a lOOO~N size, as explained in the description of' the AT instruction.
The following program would cause the rectangle to be exposed by the electron beam system:
RE 1 Xl Yl X2 Y2 J A
RE is a mnemonic for rectangle. The parameter -1 means that the coordinate~ used are in grid units. The coordinates Xl,Yl specify the point 96 while the coordinates X2,Y2 speci~y the point 98. Since the shape is a rectangle 9 by specifying kwo diagonal corners, the remaining two points 100 and 102 are also specified7 If the paramPter J is equal to one, only the outline of the rectangle will be exposed. The outline will have a width equal to the aperturs. If J is equal to zero, the entire area of the rectangle will be exposed. If the parameter A is zero~ the rectangle will have the size specified by the four points 96-102.
If A is a one, the size of the rectangle will be increased by the aperture size, i.e., one half of the aperture size along each side ~pecified by the four points 96~102.
EYery rectangle in the master slice i5 defined using either the 9x6 micron grid or the 9x9 micron grid shown in FIGURE 2. FIGURE 6 shows that the location of the rectangle can be changed by changing the grid and the size of a rectangle can be changed by changing either the grid or the aperture size.
Thus, the invention allows any feature of the design to be 3~

changed by changing a rew s~a~emenks in the program. Rectangle size~, and the spacing between rectangles, can be changed by changing the column and row definition of the grid with the OR 3 statement of TABLE 4, or the size only can be changed by changing the aperture size with the AT statement of TABLE 3, while the DI 3 statement of TABLE 4 can change the increment of movement of the electron beam sy~tem if the size of the spot has to be changed.
FIGURES 7 through 10 are flow charts showing how the programs utilize the present invention to genera~e an output for an electron beam system that will expose the masks. These figures are explained in the following paragraphs~ The term LIBF as used in the figures and in the de~cription, is a library function consisting of executable statements (instructions). A LIBF is analogous to a subroutine and is "called" with a DO statement. LIBFs can be nested 7 that is, a DO LIBF statement can be a statement within another LIBF~ As indicated in the flow charts, the program consists of a large number if LIBFs.
FIGURE 7 is a flow chart illustrating how the LIBFs are loaded into the computer memory. APTBL 110 is the aperture table, which will be loaded by the programO The remaining four circles 112-118 represent the LIBFs of a chip design. The basic block library 112 contains the LIBFs that define the basic block of the master slice.
The logic cell library 114 contains the LIBFs for all the cells ~hat can be used in the chip design. The chip design library 116 contains the LIBFs that describe the input/output buffers and the shift registers used for testing, that is, the librar3 contains all the standard circuitry of the chip other than the basic block. The DA (Design Automation) output library 118 contains the LIBFs that will interconnect the cells and other circuitry to give the chip its personality.
The LIBFs are read ard compiled one at a time. The name and starting address of each LIBF i5 stored in the location equivalency table (LET~ 120. As tbe LIBFs are being exscuted to generate the design of a layer, the LET 120 is used to find the starting address of a LIBF whenever a DO LIBF statement is executed~
FIGURE 8 is a flow chart showing how the LIBFs for a particular layer are executed. The scale, i.e., increment of movement, is set by a DI 3 statement in the block 1220 The grid used is set by the COL and ROW parameters of an OR 3 statement in the block 124. The aperture table 128 is loaded by the LIBF APTBL is the block 126. In the preferred embodiment, the LIBF APTBL is shown as the series of statements in TABLE 3 which load the aperture table with a set of apertures, dependent upon the layer number specified in the block 121.
The remai~der of FIGURE 8 shows how two LIBFs, LIBF CHIP 128 and LIBF CELL 130, are executed. As can be seen, LIBF CELL 130 is nested within LIBF CHIP 128~ Apertures are selected and rectangles are defined, dependent upon the layer number, as shown by the blocks 132-136.

~2 ~3~

FIGURE 9 is a flow chart showing how a LIBF i~ executed.
During the execution of LIBF A 138, the statement D() LIBF B is executed. Thus, LIBF B is nested within LIBF A~ A D0 statement can cbange tb~ origin and the flip and rotate parameters, so the new values, if any, are saved by the blocks 142-144. The starting address o~ LIBF B 140 is found in the LET 120 by the block 146.
The address of the next statement is LIBF A 138, ADD A, is saved in the LIBF stack 148 by the block 150. Parameters being used by LIBF A which might be changed during the execution of LIBF are al~o savedO These parameters include the origin, the flip and rotate parameters, the scale, and the grid. The statements of LIBF
B 140 are then executed by the block 152 until the end of the LIBF
is encountered.
The return address to LIBF A 138 and the saved parameters are found in the LIBF stack 148 by the block 154~ The parameters are reset to the saved values by the block 156-158 and the first statement in LIBF A 138, following the D0 LIBF B is executed by the block 160.
FIGURE 10 is a flow chart showing how a statement for exposing a rectangle is compiled by the program to generate the data for the electron beam system~ The previously set values, i.e. 9 parameters set by previously executed statements are shown at khe upper right o~ the figure.
The statement to be compiled is read from the file by block ~L2~3~

170. The statement is an RE statement whose parameter3 were explained previously in the description of FIGURE 6c. The stat0ment specifies that the coordinates are in grid units~ that the lower left hand corner is at Xl,Yl=2,1 grid units and that the upper right hand corner is at X2,Y2=5,5 grid units. The entire rectangle is to be exposed and its size is to be increased by the size of the aperture, The center of the rectangle 9 XCC ~ YCC iS calculated in block 172. The number o~ microns per COLUMN grid and Xl and X2 are used to calculate XCC while the number of microns per ROW grid and Yl and Y2 are used to calculate YCC.
The X and Y length of the rectangle, XLA,YLA is calculated in block 174. The same parameters that were used to calculate XCC,YCC
are used to calculate XLA,YLA.
The aperture code for the previously defined aperture n~mber five is taken from the aperture table by block 178. The aperture code type iB determined by block 180. The size of the aperture is calculated by block 182. The aperture is specified as 3007. The code of 3 specifies a square and therefore XA=YA=7.0 microns.
Since the RE statement specifies that the size of the rectangle is to be ircreased by the size of the aperture, the new X and Y
length are calculated in block 184. This is done by adding the values of XA and YA to XLA and YLA, respectively.
The rotate parameter R was previously defined to be a one, ~3~

indicating that the rectangle is ~o be rotated 90 degrees. That is, it is to be rotated 90-degrees counter clockwise about the previously defined relative origin XO~YO. The center of the rectangle with respect to the chip origin, after rotation with respect to XO, YO, is calcula~ed by block 186. Since a rotation is to be done, the X and Y lengths are interchanged by block 188~
The previously defined scale factor is used by block 192 to convert microns into spots. The data describing the rectangle is shown in block 194. The X center, Y center, X length, and Y ]ength are in spots and will be processed by another progr~m to convert them into commands suitable for controlling the electron beam system.
FIGURE 11 shows the location of the rectangle with respect to the origin of the chip, O,O, and with respect to a relative origin at 50,100. Also shown are the various X and Y coordinates derived by the program of FIGURE 10~
TABLE 5, shown below, contain a sample program listing of the library function BLOCK which is used to generate the mask patterns discussed in the description of FIGURE 1. Each time the library function is entered ? previously defined parameters, as explained in the description of FIGURE 10, determine where the rectangles are to be positioned~
The library function consists of BR (branch) statements which check for the layer number, AP (aperture) statements ~hich select an aperture from the aperture table, and AR and RE statements which ~3~

dePin~ rectangle shapes.
The ~irst BR ~tatement checks for layer 3 or 6. If the layer number agrees, aperture 2 is selected and a 2x4 array of rec~angles is generated by the AR statement, using a previously defined grid.
The OR statement changes the grid for the remainder of the library function.
The remaining BR statements check layer numbers until a match is found with the specified layer number, Then the rectangle statements following are ~xecuted. The first RE statement for layer 1 or 4 is the one explained in FIGURE 10.
TABLE 5 further illu~trates one of the power~ul features of the invention. If the aperture sizes are changed in the aperture table (TABLE 2)~ and if the grid is changed by changing the parameters of the OR 3 statement of TABLE 5 (any number of OR 3 statements could be inserted into the library function BLOCK), the sizes of any or all of the rectangles on the masks which are used to fabricate the first six layers can be changed.
The invention as above described allow~ dimensions to be easily changed to meet the layout requiremen~s of di~ferent wafer processing lines. The invention also allows a new design and a new prooess to be developed simultaneouslyO The layout rules for the new process can be made very liberal to allow prototype chips to be made and checked out at the same time that the process is being developed and checked out. As the process i~ perfected 9 the wiring ~2~36~

rules can be tightened, and the invention can be used to easily change the masks. The resulting chips, being smaller, will be ~aster, and the sf~ects of the in¢reased speed on the design can be analysed. The ability to develop both the process and the design simultaneously greatly reduces the overall development time.

PROGRAM LISTING OF BLOCK

LF BLOCK LIBF Basic circuit Block BR 2030060 Poly Pads OR 3 1 1 9 6 +1 1 Change to 9um x 6um grid BR 3010040 Field & CN~

BR 3010050 Field & CP+

3~

RE-1 7 i 11 5 0 BR2020 P-Well BR6030 Poly ~ate~
AP21 N-ch AP22 P-ch BR3060 Contact AR~3 7 1 3 2 2 6 EN BLOCK

Claims (22)

What is claimed is:

1. In an electron beam exposure system that includes means for selectively scanning an electron beam on an object in order to expose a desired pattern thereon, a method for defining the particular pattern that is to be exposed by the scanning electron beam on the object, said method comprising the steps of:
(a) defining a set of shapes that may be scanned by the electron beam;
(b) specifying each of said shapes with aperture data that defines the particular type of shape, such as line, rectangle, or square, and the relative size of the shape;
(c) defining a grid system having unit dimensions;
(d) selectively positioning a group of said shapes on said grid system so that a desired pattern is realized;
(e) generating an aperture table that contains a collection of aperture data corresponding to the group of shapes placed on the grid in step (d); and (f) using the collection of aperture data from step (e) to control the scanning of said electron beam so that the desired pattern is exposed on said object.

2. The method as defined in claim 1 wherein the relative size of the shapes as specified in the aperture data of step (b) is defined by including within the aperture data user defined units that specify the dimensions of the shape, such as the line width, the length and width of a rectangle, the length of a side of a square, and the like; and which user defined units may be readily modified and related to the unit dimensions of the grid system of step (c); whereby the dimensions of a desired pattern to be exposed by the electron beam may be readily modified to suit the requirements of a particular need.

3. The method as defined in claim 2 wherein the defining of the grid system of step (c) and the generating of the aperture table of step (e) includes a factoring in of the particular layout rules associated with the electron beam exposure system that is to be used for exposing the desired pattern; whereby the grid system and aperture table define patterns that are compatible with said layout rules; and further whereby a pattern that is compatible with a first set of layout rules may be readily converted to a pattern that is compatible with a second set of layout rules.

4. The method as defined in claim 3 wherein the collection of aperture data contained in the aperture table generated in step (e) may be scaled by an appropriate factor, thereby facilitating the covering of a pattern that is compatible with a first set of layout rules to a pattern that is compatible with a second set of layout rules.

5. The method as defined in claim 3 wherein the dimensions of each shape as specified in the aperture data of step (b) may be independently scaled.

6. The method as defined in claim 5 wherein the unit dimensions of the grid system of step (c) may be selectively scaled, whereby the overall pattern size can be altered.

7. The method as defined in claim 3 wherein the method is executed under the control of a computer, and further wherein a program language is used by said computer to define the set of said shapes that may be included within a given pattern and to generate said aperture table to define the collection of shapes that make up the given pattern.

8. The method as defined in claim 7 wherein a plurality of aperture tables may be generated by said computer, each aperture table defining a pattern that is to be exposed on an integrated circuit chip during a given process step of the fabrication of said chip on said electron beam system.

9. The method as defined in claim 8 wherein the computer program includes the capability of:
(1) positioning a given pattern in a desired location on the integrated circuit chip;
(2) combining a plurality of said patterns to form a cell on the integrated circuit chip;
(3) positioning a given cell in a desired location;
(4) scaling a given cell to a desired size;
(5) flipping a desired cell to realize a mirror image of the original cell pattern; and (6) rotating a desired cell to achieve a desired orientation of the cell pattern with regard to other cell patterns included on the integrated circuit chip.

10. The method as defined in claim 9 wherein the computer program further includes the capability of nesting the data that defines each pattern and cell in a hierarchical fashion so that all of the patterns and cells associated with an integrated circuit chip may be defined by using the grid system defined in step (b) and an aperture table as generated in step (e).

11. A system for defining the patterns to be exposed on an integrated circuit chip by an electron beam system, said electron beam system including means for selectively scanning the integrated circuit chip with an exposing electron beam in response to control signals, said pattern defining system comprising:
means for defining a set of shapes that may be scanned by said electron beam;
means for specifying the location on the chip where a particular shape defined by said defining means is to be scanned;
means for combining a plurality of said shapes at specified locations to define a desired pattern; and means for converting the defined pattern to appropriate control signals that cause the electron beam system to expose the desired pattern on the integrated circuit chip.

12. A system as defined in claim 11 wherein said defining means includes an aperture data word for each shape to be defined, said aperture data word specifying:
(1) the type of shape to be scanned, such as a line, a rectangle, or a square, and (2) the relative size of the shape to be scanned.

13. A system as defined in claim 12 wherein the types of shapes to be scanned include:
(1) lines of a specified width having short ends;
(2) lines of a specified width having long ends;
(3) squares of a specified size; and (4) rectangles having a specified length and width.

14. A system as defined in claim 13 wherein the types of shapes to be scanned further include:
(5) notched pads comprising two rectangles having a specified length and width with centers at the same location, with one rectangle being rotated approximately 90° from the other rectangle.

15. A system as defined in claim 12 wherein the relative size of the shapes to be scanned is specified in integer units, each integer unit being relatable to a specific linear dimension.

16. A system as defined in claim 12 wherein said specifying means comprises a grid system having unit dimensions, said unit dimensions being relatable to the relative size of the shape to be scanned.

17. A system as defined in claim 16 wherein the combining means comprises:
means for laying out selected shapes on said grid system so as to form a desired pattern; and means for compiling the aperture data words corresponding to the selected shapes of the desired pattern into an aperture table.

18. A system as defined in claim 17 wherein said lay out means includes a set of layout rules for the particular electron beam system on which the patterns are to be exposed, said rules including minimum acceptable requirements for spacing between shapes, line widths, and the like.

19. A system as defined in claim 18 wherein the aperture table corresponding to a pattern layed out according to a first set of layout rules may be readily modified to a pattern corresponding to a second set of layout rules.

20. A system as defined in claim 19 wherein the modification of the aperture table includes scaling of all the aperture words contained therewithin by an appropriate scaling factor, whereby the overall size of the pattern defined by the aperture table may be modified.

21. A system as defined in claim 19 wherein the modification of the aperture table includes selective adjustment of the aperture words contained therewithin, whereby individual sections of the pattern defined by the aperture table may be selectively modified.

22. A system as defined in claim 17 wherein a separate aperture table may be defined for each pattern that is to be exposed on the integrated circuit chip, each aperture table being generated from a common set of aperture words.