US20050280150A1 - Photolithographic techniques for producing angled lines - Google Patents

Photolithographic techniques for producing angled lines Download PDF

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US20050280150A1
US20050280150A1 US11182139 US18213905A US2005280150A1 US 20050280150 A1 US20050280150 A1 US 20050280150A1 US 11182139 US11182139 US 11182139 US 18213905 A US18213905 A US 18213905A US 2005280150 A1 US2005280150 A1 US 2005280150A1
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lines
orthogonal
reticle
image
non
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Paul Farrar
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Micron Technology Inc
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Micron Technology Inc
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/20Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/76Patterning of masks by imaging
    • G03F1/78Patterning of masks by imaging by charged particle beam [CPB], e.g. electron beam patterning of masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Exposure apparatus for microlithography
    • G03F7/70375Imaging systems not otherwise provided for, e.g. multiphoton lithography; Imaging systems comprising means for converting one type of radiation into another type of radiation, systems comprising mask with photo-cathode
    • G03F7/70383Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Exposure apparatus for microlithography
    • G03F7/70483Information management, control, testing, and wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management and control, including software
    • G03F7/70533Controlling abnormal operating mode, e.g. taking account of waiting time, decision to rework, rework flow
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174Particle-beam lithography, e.g. electron beam lithography
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30Electron or ion beam tubes for processing objects
    • H01J2237/304Controlling tubes
    • H01J2237/30472Controlling the beam
    • H01J2237/30483Scanning
    • H01J2237/30488Raster scan
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
    • Y02P90/26Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] characterised by modelling or simulation of the manufacturing system
    • Y02P90/265Product design therefor

Abstract

The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position θ1. The reticle is adjusted to a second rotational position θ2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position θ2. The second image is non-orthogonal with respect to the first image. Other aspects are provided herein.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • [0001]
    The present application is a continuation of U.S. application Ser. No. 10/215,214, filed Aug. 8, 2002, which is incorporated herein by reference.
  • [0002]
    This application is related to the following commonly assigned U.S. patent application which is herein incorporated by reference in its entirety: “Three Terminal Magnetic Random Access Memory,” Ser. No. 09/940,976, filed on Aug. 28, 2001.
  • TECHNICAL FIELD
  • [0003]
    This disclosure relates generally to integrated circuits, and more particularly, to semiconductor photolithographic processes.
  • BACKGROUND
  • [0004]
    Photolithographic processes in the semiconductor industry use raster scanning methods to produce masks. FIG. 1 illustrates a schematic diagram of a known raster-based photolithographic system. One example of a raster-based photolithographic process is an electron beam (e-beam) process. In an e-beam system 102, for example, a reticle 104 is placed on a table 106 which provides a motion to the reticle along a Y axis using a data set 108 and a worktable motion control module 110, and an electronic beam 112 sweeps back and forth along an X axis using the data set 108 and an e-beam control module 114 to provide a raster motion. The system performs raster-based imaging by sweeping the e-beam back and forth along the X axis, turning the e-beam on over designated areas and off until the next designated area, and appropriately stepping the worktable along the Y axis.
  • [0005]
    Raster-based photolithographic processes are limited to generating only orthogonal line patterns. With respect to an e-beam system, for example, the size of images is limited to integer multiples of the e-beam spot size. The e-beam spot size can be considered to be a pixel of the pattern. A series of stepped images is used to form lines at non-orthogonal angles with respect to a base direction.
  • [0006]
    FIG. 2 illustrates a stepped angled image formed using the known raster-based photolithographic system of FIG. 1. In this figure, parallel non-orthogonal lines are drawn at an angle of about 45° with respect to the base direction, which functions as a reference. The pattern is built by writing a spot 203 in the X direction, a spot 205 in the Y direction, a spot 207 in the X direction, and so on.
  • [0007]
    One problem associated with forming non-orthogonal lines using a raster-based photolithographic process is that the non-orthogonal lines require a larger area than the orthogonal lines. Although the minimum horizontal or vertical line width is equal to an e-beam spot size (pixel), the stepped 45° line (a slope of 1:1) requires two pixels 209 and 211, and the space between parallel 45° lines also requires two pixels 213 and 215. In an image containing parallel 30° lines, for example, even more space is required for the lines and the space between the lines.
  • [0008]
    Another problem associated with forming non-orthogonal lines using a raster-based photolithographic process is that the lines are formed with uneven edges. Although some smoothing of line edges occur during the exposure and development of the mask, the line might not smooth completely depending on the resist sensitivity. The result is an uneven line edge.
  • [0009]
    Other problems associated with forming non-orthogonal lines using a raster-based photolithographic process involve the use of more metal to form a stepped diagonal line than a minimum width diagonal line. Additionally, writing stepped images which requires a number of e-beam sweeps is less efficient than writing an orthogonal line that requires only one sweep.
  • [0010]
    Most semiconductor chip layouts are successfully designed using orthogonal lines. When a small number of non-orthogonal lines are required in a layout, they have been formed using stepped images. However, the problems associated with using stepped images to form non-orthogonal lines are exacerbated when a design requires more non-orthogonal lines to be formed in a smaller space.
  • [0011]
    Therefore, there is a need in the art to provide improved photolithographic techniques to form angled lines.
  • SUMMARY
  • [0012]
    The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject mater provides improved photolithographic techniques to form non-orthogonal (angled) lines on workpieces such as wafers and reticles. The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines (a minimum width corresponding to a pixel or e-beam spot, for example) so as to promote higher density designs, to be formed with even line edges, and to be formed efficiently.
  • [0013]
    Various embodiments of the preset subject matter involve forming non-orthogonal lines on a reticle. The non-orthogonal lines in the reticle result in non-orthogonal lines in a wafer. Various embodiments of the present subject matter involve rotating the relative position between a wafer and a reticle (by rotating the wafer and/or reticle) to form non-orthogonal lines on the wafer using orthogonal lines on the reticle. Various embodiments of the present subject matter involve directly writing non-orthogonal lines on a rotated wafer.
  • [0014]
    One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position θ1. The reticle is adjusted to a second rotational position θ2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position θ2. The second image is non-orthogonal with respect to the first image.
  • [0015]
    One aspect of the present subject matter relates to a method for forming an integrated circuit metallization layer using a damascene process and direct write raster-based photolithographic system using an electron beam or other similar means. According to various embodiments of this method, an insulator layer is deposited on a wafer, and a layer of resist is deposited on the insulator layer. A first image corresponding to a first data set is formed on the layer of resist when the wafer is at a first rotational position θ1 with respect to a reference. The wafer is adjusted to a second rotational position θ2 with respect to the reference. A second image corresponding to a second data set is formed on the first layer of resist when the reticle is at a second rotational position θ2. The second image is non-orthogonal with respect to the first image. The first image and the second image are developed, and the wafer is processed using a damascene metal fill to form a metallization layer based on the developed first image and the developed second image.
  • [0016]
    One aspect of the present subject matter relates to a method for forming integrated circuit metallization layers. According to various embodiments of the method, a first metal layer is deposited on a wafer, and a first layer of resist is deposited on the first insulator layer. A first image corresponding to a first data set on a first reticle is formed on the layer of resist when the wafer is at a first rotational position θ1 with respect to a reference. The first image is developed, and the wafer is processed to form a portion of the first metallization layer based on the developed first image. A second resist layer is deposited over the first metallization layer. A second reticle is registered to a second rotational position θ2 with respect to the reference. A second image corresponding to a second data set is formed on the second layer of resist when the wafer is at the second rotational position θ2. The second image is non-orthogonal with respect to the first image. The second image is developed, and the reticle is processed to form a complete metallization layer based on the developed second image. This may be accomplished either by rotating the reticle with respect to the wafer or the wafer with respect to the reticle. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that non-orthogonal metallization layer can be formed when the reticle has non-orthogonal images (formed by rotating the reticle with respect to the raster-based system), can be formed by rotating the wafer or reticle with respect to the raster-based system to form non-orthogonal lines when the reticle is formed with orthogonal images, and can be formed by rotating the wafer with respect to the raster-based system and directly writing onto the wafer using the raster-based system.
  • [0017]
    One aspect of the present subject matter relates to a method for forming a magnetic random access memory (MRAM) array. According to various embodiments of the method, an image of a first wiring layer of approximately parallel conductors is formed in a first reticle. An image of a second wiring layer of approximately parallel conductors is formed in a second reticle such that the conductors of the second wiring layer would cross with the conductors of the first wiring layer at a number of intersections. An image of a third wiring layer of approximately parallel conductors is formed in a third reticle such that the conductors of the third wiring layer would cross the conductors of the first wiring layer and the second wiring layer at the number of intersections. The three reticles are used to process three successive metal layers. A layer of magnetic storage elements is provided such that the storage elements are proximately located to the intersections and are adapted to be written by a first magnetic field produced by energized conductors in the first wiring layer, a second magnetic field produced by energized conductors in the second wiring layer, and a third magnetic field produced by energized conductors in the third wiring layer. At least one of the first wiring layer, the second wiring layer and the third wiring layer is formed after adjusting an rotational position (θ) of the reticle so as to be non-orthogonal with respect to at least one of the other wiring layers. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that a non-orthogonal metallization layer can be formed when the reticle has non-orthogonal images (formed by rotating the reticle with respect to the raster-based system), can be formed by rotating the wafer or reticle with respect to the raster-based system to form non-orthogonal lines when the reticle is formed with orthogonal images, and can be formed by rotating the wafer with respect to the raster-based system and direct writing onto the wafer using the raster-based system.
  • [0018]
    One aspect of the present subject matter relates to a raster-based photolithographic system for forming orthogonal and non-orthogonal images on reticles. According to various embodiments, the system includes an imager and a worktable adapted to function to orthogonally image a workpiece (such as a reticle or a wafer) in an X direction and a Y direction using a raster motion. The imager and the worktable also are adapted to adjust a rotational position of the workpiece with respect to the raster motion. The system further includes a database, and an X-controller, a Y-controller, and a θ-controller. The database includes a first data set for writing an orthogonal image with respect to the raster motion and a second data set corresponding for writing a non-orthogonal image with respect to the raster motion. The X-controller is adapted to control imaging of reticles or direct writing of wafers in an X direction. The Y-controller is adapted to control imaging of reticles or direct writing of wafers in a Y direction. The θ-controller is adapted to control an adjustment of the rotational position of the workpiece (reticle or wafer) with respect to the raster motion.
  • [0019]
    These and other aspects, embodiments, advantages, and features will become apparent from the following description of the present subject matter and the referenced drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0020]
    FIG. 1 illustrates a schematic diagram of a known raster-based photolithographic system.
  • [0021]
    FIG. 2 illustrates a stepped angled image formed using the known raster-based photolithographic system of FIG. 1.
  • [0022]
    FIG. 3 illustrates a schematic diagram of a raster-based photolithographic system according to various embodiments of the present subject matter.
  • [0023]
    FIG. 4 illustrates an angled image formed according to various embodiments of the present subject matter using the raster-based photolithographic system of FIG. 3.
  • [0024]
    FIG. 5 illustrates a schematic representation of a first image formed on a reticle using a first data set in a raster-based photolithographic system.
  • [0025]
    FIG. 6 illustrates a schematic representation of a second image formed on a rotated reticle (after the first image is formed in FIG. 5) using a second data set in the raster-based photolithographic system.
  • [0026]
    FIG. 7 illustrates a MRAM according to various embodiments of the present subject matter with magnetic memory cells or storage devices located at intersections among bit lines, word lines and select lines in a cross point array.
  • [0027]
    FIG. 8 illustrates an intersection in the cross point array of FIG. 7 in more detail.
  • [0028]
    FIG. 9 illustrates a structure for various embodiments of the cross point array of FIG. 7.
  • [0029]
    FIGS. 10A, 10B and 10C illustrate horizontal word lines, angled select lines, and angled bit lines, respectively, formed using the known raster-based photolithographic system of FIG. 1.
  • [0030]
    FIGS. 11A, 11B and 11C illustrate horizontal word lines, non-orthogonal select lines, and non-orthogonal bit lines, respectively, formed according to various embodiments of the present subject matter using the raster-based photolithographic system of FIG. 3.
  • [0031]
    FIG. 12 is a simplified block diagram of a high-level organization of various embodiments of an electronic system according to the present subject matter.
  • [0032]
    FIG. 13 illustrates a method for forming non-orthogonal images in a raster-based photolithographic system according to various embodiments of the present subject matter.
  • [0033]
    FIG. 14 illustrates a method for aligning the second image with the first image according to various embodiments of the method illustrated in FIG. 13.
  • [0034]
    FIG. 15 illustrates a method for aligning the first image and the second image with the reticle according to various embodiments of the method illustrated in FIG. 13.
  • [0035]
    FIG. 16 illustrates a method for forming an integrated circuit metallization layer according to various embodiments of the present subject matter.
  • [0036]
    FIG. 17 illustrates a method for forming integrated circuit metallization layers according to various embodiments of the present subject matter.
  • [0037]
    FIG. 18 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter.
  • [0038]
    FIG. 19 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter.
  • [0039]
    FIG. 20 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter.
  • DETAILED DESCRIPTION
  • [0040]
    The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present subject matter is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • [0041]
    The term “substrate” used in the following description may include any semiconductor-based structure that has an exposed surface. The structure may include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-germanium, germanium, or gallium arsenide. A wafer is a slice of semiconductor material from which chips are made, and thus form a substrate. When reference is made to a wafer or substrate in the following description, previous process steps may be utilized to form regions, junctions, or layers in or on the base semiconductor or foundation.
  • [0042]
    One definition of raster is a scan/write pattern in which an area is scanned/written from side to side in lines from top to bottom (or bottom to top). A raster-based photolithographic system, such as an e-beam system, writes an image on a line along an X axis, increments to a new line along a Y axis, writes an image on the new line, and so on to form the overall image. Since the degrees of motion lie in the X direction and the Y direction, the raster-based photolithographic system provides orthogonal images. Orthogonal images are images that, at their smallest pixel level, involve orthogonal lines along the X axis and the Y axis. As is known in the art such raster based electron beam systems are used to produce the reticles used in the modern step and repeat and step and scan photo tools. They are also used in direct write electron beam expose tools.
  • [0043]
    The present subject matter effectively rotates a workpiece such that non-orthogonal images are capable of being written on the workpiece. In various embodiments, the present subject matter effectively rotates the reticle blank such that non-orthogonal images are capable of being written on the reticle. In various embodiments, the reticle is rotated with respect to the orthogonal directions of motion for the e-beam and the worktable.
  • [0044]
    In various embodiments, the present subject matter effectively rotates a wafer such that non-orthogonal images are capable of being directly written on the wafer. In various embodiments, the wafer is rotated with respect to the orthogonal directions of motion for the e-beam and the worktable.
  • [0045]
    In various embodiments, the present subject matter effectively rotates the mask such that non-orthogonal images are capable of being written on the wafer. In various embodiments, the wafer is rotated with respect to the orthogonal directions of the mask axes.
  • [0046]
    FIG. 3 illustrates a schematic diagram of a raster-based photolithographic system according to various embodiments of the present subject matter. The illustrated system 302 includes a worktable 306 which is adapted to receive a reticle 304 and to provide a linear motion to the reticle along a Y axis using a data set 308 (such as may be contained in a programmable computer) and a worktable control module 310. The illustrated system 302 also includes an electronic beam 312 that sweeps back and forth along an X axis using the data set 308 and an e-beam control module 314 to perform the raster scan. One of ordinary skill in the art will understand the system 302 includes the required technology to produce and focus the electronic beam 312.
  • [0047]
    The worktable 306, or holder, of the reticle 302 is capable of linear motion (i.e. Y axis motion) and, according to various embodiments, is capable of having a rotational angle (θ) adjusted. Thus, the worktable 306 is capable of being at a first predetermined rotational position θ1 for imaging orthogonal lines on the reticle, and is capable of being at a second predetermined rotational position θ2 for imaging non-orthogonal lines on the reticle. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that a number of systems are capable of being used to provide the reticle 302 with a desired rotational position.
  • [0048]
    According to various embodiments, the worktable 306 is capable of being at a number of other rotational positions. According to various embodiments, the worktable is capable of being accurately moved or stepped through a number of rotational positions from rotational position θ1 to rotational position θ2. In various embodiments, the worktable motion control module 310 is adapted to control the rotational motion and position of the reticle 302. In various embodiments, a registration sensor system 321 is used to accurately detect the position of the reticle, and to work with at least one of the control modules 310 and 314 to adjust the position of the reticle 304 or otherwise register the image on the reticle. For example, the registration sensor system 321 is capable of finely adjusting the rotation of the worktable and/or adjusting the deflection of the e-beam such that a number of images are accurately printed with respect to each other.
  • [0049]
    One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the superimposed chip image is sized and/or designed to fit in the usable area of the reticle 302 regardless of the rotational position of the reticle. The chip image pattern is produced using at least two data sets 316 and 318. A first data set 316 is used to pattern first images (e.g. orthogonal images) when the reticle 304 is at a first rotational position θ1. The orthogonal images, for example, can be viewed as having horizontal and vertical directions that are consistent with previous chip levels. A second data set 318 is used to pattern second images (non-orthogonal or angled) when the reticle is at a second rotational position θ2. Additional data sets (N) 320 are capable of being used to pattern non-orthogonal images when the reticle is at an Nth rotational position θN. The data sets are operated on by a programmable computer to provide the image patterns. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the superimposed chip image may be formed either directly on a wafer or other substrate, or on a reticle which will be used to expose a wafer or other substrate.
  • [0050]
    FIG. 4 illustrates an angled image formed according to various embodiments of the present subject matter using the raster-based photolithographic system of FIG. 3. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the resulting non-orthogonal image has angled lines with even edges, and that the lines and the spaces are imaged to a minimum thickness corresponding to the dimensions of the e-beam spot. Additionally, each of the lines are capable of being formed with one e-beam scan motion, and as such are efficiently formed.
  • [0051]
    Raster-based photolithographic systems are capable of aligning sub-fields to, for example, place two or more chip images on a single reticle. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to register a reticle to accurately image a number of sub-fields with respect to each other. Thus, one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to align the first image corresponding to the first data set 316 with the second image corresponding to the second data set 318.
  • [0052]
    FIG. 5 illustrates a schematic representation of a first image formed on a reticle using a first data set in a raster-based photolithographic system. In the illustrated embodiment, the area 524 of the first data set (less the alignment markings) corresponds with the usable area of the reticle.
  • [0053]
    According to various embodiments, alignment markings 522 on the reticle 524 are used to properly position the image produced by the second data set with the image produced by the first data set. In various embodiments, for example, the alignment markings are included in the first data set and are incorporated in the orthogonal first image. Thus, the markings 522, the vertical lines 526 of the orthogonal first image, and the horizontal lines 528 of the orthogonal first image are imaged or printed together. These alignment markings 522 from the first data set are used to align the second image that corresponds to the second data set.
  • [0054]
    In various embodiments, for example, the alignment markings 522 are preprinted or otherwise incorporated on the reticle 524. These preprinted alignment markings 522 are used to properly position the image of the first data set and are used to properly position the image of the second data set.
  • [0055]
    In various embodiments, for example, the alignment markings 522 include crosses at each corner of the chip. In various embodiments, the crosses are positioned on a line that bisects the corner angle of the reticle/chip. One of ordinary skill in the art will understand that other alignment markings are able to be used, and that other methods for registering the position of the reticle are anticipated. In various embodiments, the registration sensor system 321 of FIG. 3 is used to accurately detect the position of the reticle, and to function with at least one of the control modules 310 and 314 to adjust the position of the reticle 304 or otherwise register the image on the reticle.
  • [0056]
    FIG. 6 illustrates a schematic representation of a second image formed on a rotated reticle (after the first image is formed in FIG. 5) using a second data set in the raster-based photolithographic system. The second data set is rotated with respect to the first data set so that the angled lines are vertical/horizontal lines 630 with appropriate alignment markings 632. The alignment markings 632 are coincident with the alignment markings 522 (shown in FIG. 5) when superimposed on the first data set.
  • [0057]
    The total area of the second data set is shown via line 634. However, there is no data (i.e. lines) outside of the area 624 of the rotated first data set, except for the alignment markings 632. The imaged lines 630 from the second data set are illustrated to connect the imaged lines from the first data set.
  • [0058]
    In the illustrated embodiment, the exposure field of the e-beam system is as large as area 634 for the second data set, including the alignment markings. The reticle size needs only be as big as the first data set, including the alignment markings.
  • [0059]
    The actual production of the reticle can be done on a number of ways, depending upon the type of alignment system used to align the e-beam fields. In various embodiments, the first data set is printed upon the resist on the plate, and the plate is removed from the system and the resist is developed and the plate metallurgy etched. A new layer of resist is applied, the plate is placed back in to the system in a rotated position, and data set two is aligned to the alignment markings. The resist is developed and the plate metallurgy etched.
  • [0060]
    In various embodiments, alignment markings are pre-positioned on the reticle prior to the first exposure. In this system, the two data sets are aligned to the pre-positioned alignment markings. The first data set is used followed by the required mask rotation and then the second data set is used for the second exposure.
  • [0061]
    One or ordinary skill in the art, upon reading and comprehending this disclosure, will understand that a process sequence similar to the sequence used in the illustrated production of a reticle in FIGS. 5 and 6 can be used in the raster beam direct write of a wafer or other substrate. Additionally, one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to rotate the relative position of the wafer with respect to the reticle to produce non-orthogonal lines on the wafer when the reticle has an orthogonal image.
  • [0062]
    The systems and methods of the present subject matter are capable of being used to form a magnetic random access memory (MRAM) array such as that provided by the patent application entitled “Three Terminal Magnetic Random Access Memory,” Ser. No. 09/940,976, filed on Aug. 28, 2001, which was previously incorporated by reference in its entirety. As discussed therein, the three terminal MRAM significantly diminishes half-select errors by energizing three lines (a word line, a bit line and a select line) rather than two lines to access a selected bit. At least one of the three lines is non-orthogonal with respect to the other lines. FIGS. 7-9 illustrate various aspects for forming a three terminal magnetic random access memory.
  • [0063]
    FIG. 7 illustrates a MRAM with magnetic memory cells or storage devices located at intersections among bit lines, word lines and select lines in a cross point array. The illustrated MRAM 740 includes Word Line Control Circuitry 742, Bit Line Control Circuitry 744, and Select Line Control Circuitry 746. These control circuits control the current direction and magnitude on the conductors, cooperate with each other to write to a desired magnetic storage device by providing the appropriate current to a word line conductor 750, a bit line conductor 752, and a select line conductor 754 that corresponds to the desired magnetic storage device 756. The magnetic storage device is capable of being magnetically coupled to a magnetic field generated by current in the word line, bit line and select line conductors.
  • [0064]
    According to various embodiments, the word line conductors are oriented at an angle of approximately 60° with the bit line conductors and the select line conductors, and the bit line conductors are oriented at an angle of approximately 60° with the select line conductors. The MRAM 740 is characterized as a three terminal MRAM, as it includes requires a terminal to control the word line conductors 750, a terminal to control the bit line conductors 752, and a terminal to control the select line conductors 754. All three conductors are energized to write to a desired memory cell 756.
  • [0065]
    FIG. 8 illustrates an intersection in the cross point array in more detail. This intersection represents a memory cell, and includes a magnetic storage element 856, a word line conductor 850, a bit line conductor 852, and a select line conductor 854.
  • [0066]
    FIG. 9 illustrates a structure for one embodiment of the cross point array of FIG. 7. In this embodiment, a properly insulated magnetic storage element 956 is interposed between a bit line 952 and a word line 950 at each intersection. A select line 954 also passes operably close to the magnetic storage element 956 at the intersection. According to various embodiments, the array is fabricated by forming or otherwise providing a word line layer, a storage element layer on the word line layer, a bit line layer on the storage element layer, an insulator layer 958 on the bit line layer, and a select line layer on the insulator layer. The magnetic storage element is capable of being magnetically coupled by a magnetic field generated by a current in each of these layers. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that other structural designs are capable of being used to magnetically couple the magnetic storage element 956 with the magnetic fields produced by energizing the three lines. According to various embodiments, the magnetic storage element is a magnetoresistance device, and is electrically coupled to the word line and the bit line.
  • [0067]
    FIGS. 10A, 10B and 10C illustrate horizontal word lines, angled select lines, and angled bit lines, respectively, formed using the known raster-based photolithographic system of FIG. 1. FIGS. 10A, 10B and 10C are stacked together to form the array shown in FIG. 7. The word lines 1050 of FIG. 10A, the select lines 1054 of FIG. 10B, and the bit lines 1052 of FIG. 10C form metallization layers, and cross each other at intersections such as is illustrated in FIGS. 7-9.
  • [0068]
    The angled select lines 1054 and the angled bit lines 1052 are stepped images, which require more than a minimum feature size to form the lines and to separate the lines. Since both the angled select lines 1054 and the angled bit lines 1052 are separated by a greater distance, the select lines 1054 and the bit lines 1052 cross and form intersections fewer times in a given area. The horizontal lines 1050 cross the angled select lines 1054 and the angled bit lines 1052 at the intersections, and thus are separated by a distance greater than a minimum distance that corresponds to the pixel width or e-beam spot width. Six word lines, six select lines and six bit lines fit within the area illustrated in FIGS. 10A-10C.
  • [0069]
    FIGS. 11A, 11B and 11C illustrate horizontal word lines, non-orthogonal select lines, and non-orthogonal bit lines, respectively, formed according to various embodiments of the present subject matter using the raster-based photolithographic system of FIG. 3. The word lines 1150 of FIG. 11A, the select lines 1154 of FIG. 11B, and the bit lines 1152 of FIG. 11C form metallization layers, and cross each other at intersections such as is illustrated in FIGS. 7-9.
  • [0070]
    The angled select lines 1154 and the angled bit lines 1152 have even edges, and are imaged to a minimum thickness corresponding to the feature size or e-beam spot. Because the parallel angled lines are separated by a minimum distance, the angled select lines 1154 and the angled bit lines 1152 cross and form intersections more times in a given area. The horizontal lines 1150 cross the angled select lines 1154 and the angled bit lines 1152 at the more densely-packed intersections, and thus are capable of being closer together. Nine word lines, ten select lines and ten bit lines fit within the area illustrated in FIGS. 11A-11C, as compared to the six word lines, six select lines and six bit lines fit within the area illustrated in FIGS. 10A-10C. Thus, the present subject matter provides more compact, three-terminal MRAM designs as compared to using stepped angled images from a conventional, raster-based photolithographic system.
  • [0000]
    System Level
  • [0071]
    FIG. 12 is a simplified block diagram of a high-level organization of various embodiments of an electronic system according to the present subject matter. In various embodiments, the system 1200 is a computer system, a process control system or other system that employs a processor and associated memory. The electronic system 1200 has functional elements, including a processor or arithmetic/logic unit (ALU) 1202, a control unit 1204, a memory device unit 1206 and an input/output (I/O) device 1208. Generally such an electronic system 1200 will have a native set of instructions that specify operations to be performed on data by the processor 1202 and other interactions between the processor 1202, the memory device unit 1206 and the I/O devices 1208. The control unit 1204 coordinates all operations of the processor 1202, the memory device 1206 and the I/O devices 1208 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 1206 and executed. According to various embodiments, the memory device 1206 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive. As one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, any of the illustrated electrical components are capable of being fabricated to include a chip produced with non-orthogonal photolithography in accordance with the present subject matter.
  • [0072]
    The illustration of system, as shown in FIG. 12, is intended to provide a general understanding of one application for the structure and circuitry of the present subject matter, and is not intended to serve as a complete description of all the elements and features of an electronic system that uses non-orthogonal photolithographic processes according to the present subject matter. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
  • [0073]
    Applications that use non-orthogonal photolithographic processes as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
  • [0000]
    Method Aspects
  • [0074]
    The figures presented and described in detail above are similarly useful in describing the method aspects of the present subject matter. The methods described below are nonexclusive as other methods may be understood from the specification and the figures described above.
  • [0075]
    FIG. 13 illustrates a method for forming non-orthogonal images in a raster-based photolithographic system according to various embodiments of the present subject matter. In the illustrated method 1300, a first image is formed at 1302 when the reticle is at a first rotational angle θ1. The first image corresponds to a first data set. For example, the first image may be formed to be orthogonal with respect to other photolithographic images on the reticle.
  • [0076]
    At 1304, the reticle is adjusted to a second rotational angle θ2. At 1306, a second image corresponding to a second data set is formed when the reticle is at the second rotational angle θ2. According to various embodiments, the difference between the angles θ2−θ1 is not 0°, 90°, 180° or 270° such that the second image is non-orthogonal with respect to the first image. According to various embodiments, the reticle is adjusted by rotating the worktable from the first rotational angle θ1 to the second rotational angle θ2. According to various embodiments, the reticle is adjusted by accurately stepping the worktable through a number of rotational positions from the first rotational angle θ1 to the second rotational angle θ2.
  • [0077]
    Additional images are formed on the reticle in various embodiments. For example, the reticle is adjusted to an Nth rotational position θN at 1308, and at 1310, an Nth image corresponding to an Nth data set is formed on the reticle when the reticle is at the rotational position θN.
  • [0078]
    One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to substitute a wafer or other workpiece for the reticle shown in FIG. 13 for a direct write electron beam or similar direct write system.
  • [0079]
    FIG. 14 illustrates a method for aligning the second image with the first image according to various embodiments of the method illustrated in FIG. 13. In the illustrated method 1412, a first image includes alignment markings, and is formed on the reticle at 1414 when the reticle is at a first rotational position θ1. At 1416, the image is positioned at a second rotational position θ2 and is registered to the alignment markings formed as part of the first image. One of ordinary skill in the art will know how to register to the reticle to the alignment markings. According to various embodiments, the reticle is rotated between the first rotational position θ1 and the second rotation position θ2. According to various embodiments, the reticle is accurately stepped through a number of rotational positions between the first rotational position θ1 and the second rotation position θ2. At 1418, a second image is formed at θ2.
  • [0080]
    FIG. 15 illustrates a method for aligning the first image and the second image with the reticle according to various embodiments of the method illustrated in FIG. 13. In the illustrated method 1520, at 1522, the reticle is positioned at a first rotational position θ1 and is registered to alignment markings already preprinted or otherwise identified on the reticle. At 1524, a first image is formed at the first rotational position θ1. At 1526, the reticle is positioned at a second rotational position θ2 and the image is registered to the alignment markings. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that in various embodiments, the image used at 1526 is a different image than that used at 1522. At 1528, a second image is formed at the second rotational position θ2.
  • [0081]
    FIG. 16 illustrates a method for forming an integrated circuit metallization layer according to various embodiments of the present subject matter. In the illustrated method 1630, an insulator is deposited on a wafer at 1632, and a resist is deposited on the insulator at 1634. At 1636, a first image is formed on the resist when the reticle is at a first rotational position θ1. At 1638, the second reticle is adjusted and appropriately registered to a second rotational position θ2. At 1640, a second image is formed on the resist when the reticle is at the second rotational position θ2. The first and second images are developed at 1642, and at 1644, the wafer is processed to form a metallization layer using the damascene process based on the developed first and second images. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the metallization layer also can be formed using subtractive etch process. Thus, a single metallization layer is capable of including both orthogonal and non-orthogonal lines.
  • [0082]
    FIG. 17 illustrates a method for forming integrated circuit metallization layers according to various embodiments of the present subject matter. In the illustrated method 1746, a first insulator is deposited on a wafer at 1748, and a first resist is deposited on the first insulator at 1750. At 1752, a first image is formed on the resist when the first reticle is at a first rotational position θ1. The first image is developed at 1754, and at 1756, the wafer is processed to form a first metallization layer using the damascene process based on the developed first image. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the wafer can be processed to form the metallization layer using a subtractive etch process. The damascene process and the subtractive etch process are known. Upon reading and comprehending this disclosure, those of ordinary skill in the art will understand how to incorporate the present subject with these processes.
  • [0083]
    At 1758, a second insulator is deposited on the wafer, and a second resist is deposited on the second insulator at 1760. At 1762, the process uses a second reticle which was imaged registered a second rotational position θ2. The reticle is appropriately registered to the first level. At 1764, a second image is formed on the resist. The second image is developed at 1766, and at 1768, the wafer is processed to form a metallization layer based on the developed second image. Thus, as the image on the second reticle was placed at an angle to the first, one metallization layer is capable of being non-orthogonal with respect to another metallization layer.
  • [0084]
    FIG. 18 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter. In the illustrated method, a reticle is formed with a non-orthogonal image at 1870. According to various embodiments, the non-orthogonal image is formed on the reticle by rotating or otherwise adjusting the reticle to a desired rotational position, and forming the non-orthogonal image on the rotated reticle using a raster-based photolithographic system. At 1872, the non-orthogonal lines are formed on the substrate/wafer using the reticle.
  • [0085]
    FIG. 19 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter. In the illustrated method, at 1974 a reticle is formed with an orthogonal image using a raster-based system. The relative position between the reticle and the substrate/wafer is registered at 1976. In various embodiments, the reticle is rotated to register the relative position. In various embodiments, the substrate is rotated to register the relative position. At 1978, non-orthogonal lines are formed on the substrate/wafer using the reticle.
  • [0086]
    FIG. 20 illustrates a method for forming non-orthogonal lines on a substrate according to various embodiments of the present subject matter. In the illustrated method, a rotational position of the substrate/wafer is registered at 2080. A non-orthogonal image is directly written on the substrate at 2082.
  • CONCLUSION
  • [0087]
    The present subject mater relates to improved photolithographic techniques for forming non-orthogonal (angled) lines. The present subject matter provides a modified raster-based photolithographic process in which a rotational angle (θ) of a reticle is adjusted to change the reference of the orthogonal, raster-based system. Thus, orthogonal lines are capable of being printed using a first data set, and after θ is adjusted, non-orthogonal lines are capable of being printed using a second data set. The present subject matter allows non-orthogonal lines to be formed at the same minimum thickness as the orthogonal lines, to be formed with even line edges, and to be formed efficiently since each line is capable of being printed in a single scan.
  • [0088]
    In various embodiments, the present subject matter is used to produce reticles with non-orthogonal lines. In various embodiments, the present subject matter is used to rotate a relative position between a wafer and a reticle to produce non-orthogonal lines on the wafer from the orthogonal lines on the reticle. In various embodiments, the present subject matter is used to directly write non-orthogonal lines on a wafer.
  • [0089]
    This disclosure refers to several figures that resemble flow diagrams. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the methods related to the flow diagrams may occur in the order as illustrated in the flow diagrams, and may be ordered in another manner. Thus, the present subject matter is not limited to a particular order or logical arrangement.
  • [0090]
    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations of the present subject matter. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present subject matter should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (38)

  1. 1. A device, comprising:
    a semiconductor substrate; and
    an integrated circuit formed on the semiconductor substrate, the integrated circuit including at least a first line, a second line and a third line, the first line being oriented in a first direction, the second line being oriented in a second direction orthogonal to the first direction, the third line being oriented in a third direction that is non-orthogonal and non-parallel to both the first and second directions, the first and the second lines having a minimum design line width, and the non-orthogonal and non-parallel third line having the same minimum design line width.
  2. 2. The device of claim 1, wherein the third direction includes 45 degrees to both the first and second directions.
  3. 3. The device of claim 1, wherein the integrated circuit comprises a plurality of semiconductor devices.
  4. 4. The device of claim 3, wherein the plurality of semiconductor devices includes devices having edges that are oriented in the first and second directions, and devices having at least one edge oriented in the third direction.
  5. 5. The device of claim 3, wherein the plurality of semiconductor devices are interconnected by metal conductor lines having orientations in the first direction, the second direction and the third direction.
  6. 6. The device of claim 5, wherein the metal conductor lines include lines on more than a single level.
  7. 7. The device of claim 6, wherein the metal conductor lines include lines on three different levels, each level including a patterned insulator layer disposed beneath the level.
  8. 8. The device of claim 1, wherein the integrated circuit comprises a plurality of devices, at least one of the plurality of devices having an outline comprising straight lines in the first, second and third directions, wherein all of the straight lines are substantially smooth.
  9. 9. An integrated circuit chip, comprising:
    a semiconductive substrate; and
    a plurality of semiconductor devices formed on the semiconductive substrate, each individual one of the plurality having a shape definable by a polygon of straight lines that are substantially smooth, each of the straight lines having an orientation in one of a first direction, a second direction orthogonal to the first direction, and a third direction non-orthogonal and non-parallel to both the first and second directions, at least one of the plurality of semiconductor devices having a shape with a straight line in the third direction.
  10. 10. The integrated circuit chip of claim 9, wherein the third direction includes 45 degrees to both the first and second directions.
  11. 11. The integrated circuit chip of claim 9, wherein the straight lines in the first and the second directions have a minimum design line width, and one of the non-orthogonal and non-parallel lines in the third direction has the same minimum design line width.
  12. 12. The integrated circuit chip of claim 9, further comprising at least one minimum dimension metal conductor line in each of the first direction, the second direction and the third direction.
  13. 13. The integrated circuit chip of claim 12, wherein at least one of the minimum dimension conductor lines electrically connect at least two of the plurality of semiconductor devices.
  14. 14. The integrated circuit chip of claim 12, wherein the metal conductor lines include lines on more than a single level.
  15. 15. The integrated circuit chip of claim 14, wherein the metal conductor lines include lines on three different levels, each level including a patterned insulator layer disposed beneath the level.
  16. 16. A semiconductor wafer, comprising:
    a semiconductive substrate having a plurality of individual integrated circuits, each integrated circuit including four orthogonal sides oriented in one of a first direction and a second direction;
    each individual integrated circuit having a plurality of semiconductor devices, each individual one of the plurality of semiconductor devices having a shape definable by a polygon of straight lines, each of the straight lines having an orientation value with respect to the first direction and second direction; and
    at least one of the plurality of semiconductor devices including at least one straight line that has an orientation that is non-orthogonal and non-parallel to the first and second directions.
  17. 17. The semiconductor wafer of claim 16, wherein the non-orthogonal and non-parallel orientation is 45 degrees with respect to the first and second directions.
  18. 18. The semiconductor wafer of claim 16, wherein at least one of the semiconductor devices has at least two lines that are oriented orthogonal to one of the first and second directions, and ends of the at least two lines are connected to each other by at least one line having an orientation that is non-orthogonal and non-parallel to the first and second directions.
  19. 19. The semiconductor wafer of claim 16, wherein the plurality of semiconductor devices includes devices having a rectangular shape having sides oriented to at least one of the first and second direction, and devices having a non-rectangular shape and at least one side that is non-orthogonal and non-parallel to the first and second directions.
  20. 20. The semiconductor wafer of claim 19, wherein the plurality of semiconductor devices includes conductive interconnections having a minimum allowable width, with at least one interconnection having the minimum allowable width on each of the individual integrated circuits having an orientation that is non-orthogonal and non-parallel to first and second directions.
  21. 21. The semiconductor wafer of claim 20, wherein the non-orthogonal and non-parallel orientation is 60 degrees with respect to at least one of the orthogonal sides.
  22. 22. The semiconductor wafer of claim 20, wherein the non-orthogonal and non-parallel orientation is 30 degrees with respect to at least one of the orthogonal sides.
  23. 23. The semiconductor wafer of claim 22, wherein the metal conductor lines include lines on more than a single level.
  24. 24. The semiconductor wafer of claim 23, wherein the metal conductor lines include lines on three different levels, each level including a patterned insulator layer disposed beneath the level.
  25. 25. The semiconductor wafer of claim 16, wherein each individual one of the straight lines has edges that are substantially smooth.
  26. 26. A photolithography mask, comprising:
    a substrate having at least one pattern;
    the pattern including a first line, a second line and a third line, the first line having an orientation in a first direction, the second line having an orientation in a second direction orthogonal to the first direction, and the third line having an orientation in a third direction that is non-orthogonal and non-parallel to both the first and second directions; and
    the pattern including lines having a plurality of widths, including lines having a minimum allowable design width in each one of the first, second and third directions.
  27. 27. The photolithography mask of claim 26, wherein the orientation of the third line is approximately 45 degrees with respect to the first and second directions.
  28. 28. The photolithography mask of claim 26, wherein the at least one pattern comprises a single layer pattern of an integrated circuit chip.
  29. 29. The photolithography mask of claim 26, wherein portions of the substrate are substantially transparent to electron beams.
  30. 30. The photolithography mask of claim 26, wherein the pattern includes structures having rectangular shapes with sides parallel to one or more of the first direction and the second direction, and the pattern includes structures having at least one side having an orientation in the third direction.
  31. 31. A device, comprising:
    a work piece;
    a first line on the work piece oriented in a first direction;
    a second line on the work piece oriented in a second direction that is non-orthogonal and non-parallel to the first direction; and
    the first and second lines having a minimum photolithographic design width, and having a substantially even edge.
  32. 32. The device of claim 31, wherein the work piece includes a reticle.
  33. 33. The device of claim 31, wherein the work piece includes a wafer.
  34. 34. The device of claim 31, wherein the first line defines a first conductor line and the second line defines a second conductor line.
  35. 35. The device of claim 34, further comprising a third line on the work piece, the third line defining a third conductor line, the second line connecting the first line to the third line.
  36. 36. The device of claim 35, wherein the third line is oriented in a third direction orthogonal to the first direction.
  37. 37. The device of claim 35, wherein the third line is oriented in a direction parallel to the first direction.
  38. 38. The device of claim 31, wherein the first and second lines define first and second edges of a device shape.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026086A1 (en) * 2002-08-08 2005-02-03 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US20070235665A1 (en) * 2006-03-30 2007-10-11 Applied Materials, Inc. Charged particle beam system and method for manufacturing and inspecting LCD devices

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004023062A (en) * 2002-06-20 2004-01-22 Nec Electronics Corp Semiconductor device and method for manufacturing the same
US7583362B2 (en) * 2004-11-23 2009-09-01 Infineon Technologies Ag Stray light feedback for dose control in semiconductor lithography systems
CN101305319A (en) * 2005-09-07 2008-11-12 凸版光掩膜公司 Photomask and method for forming a non-orthogonal feature on the same
US20080035956A1 (en) * 2006-08-14 2008-02-14 Micron Technology, Inc. Memory device with non-orthogonal word and bit lines
DE112010005559T5 (en) * 2010-05-11 2013-03-21 Toyota Jidosha K.K. suspension device

Citations (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4310743A (en) * 1979-09-24 1982-01-12 Hughes Aircraft Company Ion beam lithography process and apparatus using step-and-repeat exposure
US4465934A (en) * 1981-01-23 1984-08-14 Veeco Instruments Inc. Parallel charged particle beam exposure system
US4748478A (en) * 1985-12-19 1988-05-31 Nippon Kogaku K. K. Projection exposure apparatus
US4758863A (en) * 1987-02-17 1988-07-19 Hewlett-Packard Company Multi-image reticle
US4769523A (en) * 1985-03-08 1988-09-06 Nippon Kogaku K.K. Laser processing apparatus
US5251140A (en) * 1991-07-26 1993-10-05 International Business Machines Corporation E-beam control data compaction system and method
US5446649A (en) * 1992-12-31 1995-08-29 International Business Machines Corporation Data-hiding and skew scan for unioning of shapes in electron beam lithography post-processing
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5627624A (en) * 1994-10-31 1997-05-06 Lsi Logic Corporation Integrated circuit test reticle and alignment mark optimization method
US5671173A (en) * 1994-06-10 1997-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines
US5792569A (en) * 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials
US5821592A (en) * 1997-06-30 1998-10-13 Siemens Aktiengesellschaft Dynamic random access memory arrays and methods therefor
US6178131B1 (en) * 1999-01-11 2001-01-23 Ball Semiconductor, Inc. Magnetic random access memory
US6215128B1 (en) * 1999-03-18 2001-04-10 Etec Systems, Inc. Compact photoemission source, field and objective lens arrangement for high throughput electron beam lithography
US6238850B1 (en) * 1999-08-23 2001-05-29 International Business Machines Corp. Method of forming sharp corners in a photoresist layer
US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6282113B1 (en) * 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6296977B1 (en) * 1996-12-19 2001-10-02 Nikon Corporation Method for the measurement of aberration of optical projection system
US6410948B1 (en) * 1997-08-22 2002-06-25 Micron Technology, Inc. Memory cell arrays comprising intersecting slanted portions
US6426269B1 (en) * 1999-10-21 2002-07-30 International Business Machines Corporation Dummy feature reduction using optical proximity effect correction
US6448591B1 (en) * 1995-08-14 2002-09-10 Micron Technology, Inc. Metallization line layout
US6510080B1 (en) * 2001-08-28 2003-01-21 Micron Technology Inc. Three terminal magnetic random access memory
US6522579B2 (en) * 2001-01-24 2003-02-18 Infineon Technologies, Ag Non-orthogonal MRAM device
US6581198B1 (en) * 2001-06-13 2003-06-17 Cadence Design Systems, Inc. Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring
US6671864B2 (en) * 2000-12-06 2003-12-30 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net
US6710850B2 (en) * 2000-12-22 2004-03-23 Nikon Corporation Exposure apparatus and exposure method
US6711727B1 (en) * 2000-12-07 2004-03-23 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits
US20040098696A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for routing
US6745379B2 (en) * 2001-08-23 2004-06-01 Cadence Design Systems, Inc. Method and apparatus for identifying propagation for routes with diagonal edges
US6767674B2 (en) * 2001-10-26 2004-07-27 Infineon Technologies Ag Method for obtaining elliptical and rounded shapes using beam shaping
US6769105B1 (en) * 2001-06-03 2004-07-27 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits
US20040243960A1 (en) * 2003-06-01 2004-12-02 Hengfu Hsu Methods and apparatus for defining power grid structures having diagonal stripes
US20050048741A1 (en) * 2003-09-02 2005-03-03 Phan Khoi A. Pattern recognition and metrology structure for an x-initiative layout design
US6892371B1 (en) * 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6898773B1 (en) * 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US7084413B2 (en) * 2002-08-08 2006-08-01 Micron Technology, Inc. Photolithographic techniques for producing angled lines

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3596260A (en) * 1964-03-20 1971-07-27 Sperry Rand Corp Magnetic storage device
JP3378413B2 (en) * 1994-09-16 2003-02-17 株式会社東芝 Electron beam lithography system and an electron beam drawing method
US5822214A (en) * 1994-11-02 1998-10-13 Lsi Logic Corporation CAD for hexagonal architecture
JP3950518B2 (en) * 1997-06-27 2007-08-01 キヤノン株式会社 Method for manufacturing a diffractive optical element
US6635583B2 (en) * 1998-10-01 2003-10-21 Applied Materials, Inc. Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating
US6236850B1 (en) * 1999-01-08 2001-05-22 Trw Inc. Apparatus and method for remote convenience function control with increased effective receiver seek time and reduced power consumption
US6191972B1 (en) * 1999-04-30 2001-02-20 Nec Corporation Magnetic random access memory circuit
JP2002134396A (en) * 2000-10-25 2002-05-10 Sony Corp Method for manufacturing semiconductor device and semiconductor pattern automatic regulator
KR100399436B1 (en) * 2001-03-28 2003-09-29 주식회사 하이닉스반도체 A Magnetic random access memory and a method for manufacturing the same
US7080342B2 (en) * 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US6836429B2 (en) * 2002-12-07 2004-12-28 Hewlett-Packard Development Company, L.P. MRAM having two write conductors

Patent Citations (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4310743A (en) * 1979-09-24 1982-01-12 Hughes Aircraft Company Ion beam lithography process and apparatus using step-and-repeat exposure
US4465934A (en) * 1981-01-23 1984-08-14 Veeco Instruments Inc. Parallel charged particle beam exposure system
US4769523A (en) * 1985-03-08 1988-09-06 Nippon Kogaku K.K. Laser processing apparatus
US4748478A (en) * 1985-12-19 1988-05-31 Nippon Kogaku K. K. Projection exposure apparatus
US4758863A (en) * 1987-02-17 1988-07-19 Hewlett-Packard Company Multi-image reticle
US5251140A (en) * 1991-07-26 1993-10-05 International Business Machines Corporation E-beam control data compaction system and method
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5446649A (en) * 1992-12-31 1995-08-29 International Business Machines Corporation Data-hiding and skew scan for unioning of shapes in electron beam lithography post-processing
US5671173A (en) * 1994-06-10 1997-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines
US5627624A (en) * 1994-10-31 1997-05-06 Lsi Logic Corporation Integrated circuit test reticle and alignment mark optimization method
US6448591B1 (en) * 1995-08-14 2002-09-10 Micron Technology, Inc. Metallization line layout
US5792569A (en) * 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials
US6296977B1 (en) * 1996-12-19 2001-10-02 Nikon Corporation Method for the measurement of aberration of optical projection system
US5821592A (en) * 1997-06-30 1998-10-13 Siemens Aktiengesellschaft Dynamic random access memory arrays and methods therefor
US6607944B1 (en) * 1997-08-22 2003-08-19 Micron Technology, Inc. Method of making memory cell arrays
US6410948B1 (en) * 1997-08-22 2002-06-25 Micron Technology, Inc. Memory cell arrays comprising intersecting slanted portions
US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6645842B2 (en) * 1998-06-23 2003-11-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6178131B1 (en) * 1999-01-11 2001-01-23 Ball Semiconductor, Inc. Magnetic random access memory
US6215128B1 (en) * 1999-03-18 2001-04-10 Etec Systems, Inc. Compact photoemission source, field and objective lens arrangement for high throughput electron beam lithography
US6238850B1 (en) * 1999-08-23 2001-05-29 International Business Machines Corp. Method of forming sharp corners in a photoresist layer
US6282113B1 (en) * 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6426269B1 (en) * 1999-10-21 2002-07-30 International Business Machines Corporation Dummy feature reduction using optical proximity effect correction
US6671864B2 (en) * 2000-12-06 2003-12-30 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net
US6678872B2 (en) * 2000-12-06 2004-01-13 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout
US6711727B1 (en) * 2000-12-07 2004-03-23 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits
US6710850B2 (en) * 2000-12-22 2004-03-23 Nikon Corporation Exposure apparatus and exposure method
US6522579B2 (en) * 2001-01-24 2003-02-18 Infineon Technologies, Ag Non-orthogonal MRAM device
US6895567B1 (en) * 2001-06-03 2005-05-17 Cadence Design Systems, Inc. Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
US6769105B1 (en) * 2001-06-03 2004-07-27 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits
US6854101B2 (en) * 2001-06-13 2005-02-08 Cadence Design Systems Inc. Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring
US6581198B1 (en) * 2001-06-13 2003-06-17 Cadence Design Systems, Inc. Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring
US20050091619A1 (en) * 2001-06-13 2005-04-28 Cadence Design Systems, Inc. Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring
US6745379B2 (en) * 2001-08-23 2004-06-01 Cadence Design Systems, Inc. Method and apparatus for identifying propagation for routes with diagonal edges
US6714445B2 (en) * 2001-08-28 2004-03-30 Micron Technology, Inc Three terminal magnetic random access memory
US6510080B1 (en) * 2001-08-28 2003-01-21 Micron Technology Inc. Three terminal magnetic random access memory
US6767674B2 (en) * 2001-10-26 2004-07-27 Infineon Technologies Ag Method for obtaining elliptical and rounded shapes using beam shaping
US6898773B1 (en) * 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6892371B1 (en) * 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US20060211153A1 (en) * 2002-08-08 2006-09-21 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US7084413B2 (en) * 2002-08-08 2006-08-01 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US7105841B2 (en) * 2002-08-08 2006-09-12 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US20040098696A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for routing
US20040243960A1 (en) * 2003-06-01 2004-12-02 Hengfu Hsu Methods and apparatus for defining power grid structures having diagonal stripes
US20050048741A1 (en) * 2003-09-02 2005-03-03 Phan Khoi A. Pattern recognition and metrology structure for an x-initiative layout design

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026086A1 (en) * 2002-08-08 2005-02-03 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US20050030513A1 (en) * 2002-08-08 2005-02-10 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US20050030516A1 (en) * 2002-08-08 2005-02-10 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US7105841B2 (en) 2002-08-08 2006-09-12 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US20060211153A1 (en) * 2002-08-08 2006-09-21 Micron Technology, Inc. Photolithographic techniques for producing angled lines
US7614027B2 (en) 2002-08-08 2009-11-03 Micron Technology, Inc. Methods for forming a MRAM with non-orthogonal wiring
US20070235665A1 (en) * 2006-03-30 2007-10-11 Applied Materials, Inc. Charged particle beam system and method for manufacturing and inspecting LCD devices

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US7105841B2 (en) 2006-09-12 grant

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