CA1161958A - Low resistance line - Google Patents
Low resistance lineInfo
- Publication number
- CA1161958A CA1161958A CA000348649A CA348649A CA1161958A CA 1161958 A CA1161958 A CA 1161958A CA 000348649 A CA000348649 A CA 000348649A CA 348649 A CA348649 A CA 348649A CA 1161958 A CA1161958 A CA 1161958A
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- CA
- Canada
- Prior art keywords
- region
- strip
- insulating layer
- doped
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000011248 coating agent Substances 0.000 claims description 30
- 238000000576 coating method Methods 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000001172 regenerating effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241001307210 Pene Species 0.000 description 1
- 241001131927 Placea Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A low resistance double bit line structure has doped polycrystal-line strips of one conductivity contacting a monocrystalline body of the op-posite conductivity through strip-shaped apertures in an insulating layer.
The polycrystalline material also extends from the bit lines over thin areas of the insulating layer and form memory capacitors and associated transfer electrodes.
A low resistance double bit line structure has doped polycrystal-line strips of one conductivity contacting a monocrystalline body of the op-posite conductivity through strip-shaped apertures in an insulating layer.
The polycrystalline material also extends from the bit lines over thin areas of the insulating layer and form memory capacitors and associated transfer electrodes.
Description
l9~g The invention concerns a low resistance line especially auitable for use in integrated circuits having relatively large capacities.
Such lines are used, for example, as bit lines for semiconductor memories. The problem occurs that bit lines of memories with rather large memory capacities in general are so long that as a result of the line resistance of approximately 20 to 30 Ohms/square and the line capacitance during read-in and read-out of the information which is to be stored, delay times must be taken into ac¢ount which also determine the access time of the memory.
BRIEF SUM~ARY 0~ THE INVENTION
The invention is based upon the problem of providing a line having extremely low ohmic resistance. This is attained according to the present invention by means of the measures hereinafter described.
The advantage which was aimed for with the invention especially consists in that the resistance of the double line structure which is formed out of the oppositely doped region and the contacting strip is significantly smaller than the customary diffused lines. A further design of the concept of the invention, in the case of which a transfer gate is arranged next to the low resistance line, which transfer gate is self-adjusting in its lateral position with respect to the line edge.
Thus, in accordance with one broad aspect of the invention, there is provided a low resistance line comprising a strip-shaped region which is provided on the interface of a doped semiconductor body, the strip-shaped region being doped opposite to the doped semiconductor body, characterized in that above said region, a strip of highly doped polycrystalline silicon, which con-tacts said region is located, in which said low resistance line comprises a bit line of a dynamic one-transistor memory cell, and characterized in that it is arranged in a predetermined spacing to a memory electrode which is formed out of highly doped polycrystalline sillcon, a transfer gate being provided whlch L~
1 61~
covers said region and said memory electrode at least on their boundary sides, and which is electrically insulated against the same and against said interface of said semiconductor body.
In accordance with another broad aspect of the invention there is provided an integrated circuit semiconductor memory structure, comprising, a doped monocrystalline body of a first conductivity type, an insulating thick oxide layer covering said monocrystalline body and including a row of thin oxide regions~ first and second strip-shaped apertures extending through said oxide layer and spaced apart from one another, the thin oxide regions branching off alternately from said apertures, first and second bit lines each comprising contacting strips of doped polycrystalline material of an opposite, second conductivity filling respective strip-shaped apertures, and further comprising redoped regions in said body below said strips having said opposite, second conductivity, memory electrodes carried on said thin oxide regions, being form-ed by parts of a strip of doped polycrystalline material arranged between said bit lines on said insulating thick oxide layer, an insulating layer covering said bit lines and said memory electrodes, electrodes carried on said insulat~
ing layer and laterally extending alternately from the redoped region~of one of said ~it lines toward the other over said thin oxide regions, each of said electrodes including a portion adjacent the associated bit line defining a transfer electrode, a further insulating layer covering said electrodes, a plurality of third apertures extending through said further insulating layer to said electrodes, and word lines on said further insulating layer contacting said electrodes through said third apertures.
BRIEF DESCRIPTION OF THE DRAWINGS
.
The invention will be explained more closely in the following with the use of the drawing.
Figure 1 shows a view from above upon a low reslstance llne which -la-j, . . ~ ' ~ 3 6 ~ 8 is designed according to the invention, Figure 2 shows a cross section through the line according to Figure 1, and -lb-,, 1 9~5 ~
Fi.gure 3 sh~ws a view from above onto aeveral one-transistor mem~
ory cells ~hich are driven with lines aesigned according to the invention.
DESCRIPTIO~ OF THE PREFERRED EMBODIMENTS
In Figure 1, a highly doped monocrystalline semiconauctor body 1 is sho~n, which on that portion of its periphery which lies p~rallel to the drawing plane is covered with an electrically insulating layer 2. The semi-conductor body 1 consists by way of example of p-dopea silicon, while the in~
sulating layer preferably is maae of SiO2. A strip-shaped contact hole 3 is provided which is etched out of the layer 2. A strip ~, which is ~orrned on the insulating layer 2, is made of highly doped polycrystalline silicon, the lateral limits of which in Figure 1 are indicatea by a solid line, within the contact hole 3, i8 directly adjacent to the interface of the semiconductor body 1. Beginning ~rom the contacting surfaces of these two parts, a strip-shaped semiconductor region 5 is doped opposite to the semiconductor body 1, in the present case is n+ conducting, and extends parallel to the inter~ace, the lateral limits of which are also indicated. by means of a solid line.
Figure 2 shows a cross section along the line II-II of Figure 1.
Besides the semiconductor body 1, the layer 2 ~hich is designed as a thick field oxide layer, the strip 4 which contacts the interface o~ 1 and the re-doped semiconductor region 5, underneath the thick layer 2. A zone 6 whichis directly next to the interface of the semiconductor body 1 can be seen, which zone 6 is doped more strongly than the semiconductor body 1, and has the same kind of conductivity. Such a zone can be designated as field im-plantation or ~ield diffusion. It serves the purpose of de~initively limit-ing the redoped region 5 in a lateral direction.
Together with a contacting strip 4 out of highly doped polycrystal-line silicon, the redoped region 5 represents a double line structure, the resistance in Ohms o~ which is significantly umaller than that o~ a customary -- 2 ~
1 6~9~
diffusion line. The strip 4 i8 connected via a conne~tion line 7 (Figure 1) with a lead 8, in a practical manner.
In Figure 3, four one-transistor memory cells 10 through 13 are represented which are integrated upon a monocrystalline semiconductor body 9 and which are arranged in a row. Eac~l cell is associated with a somewhat rectangular shaped thin layer region (gate oxide region) 141 tbrough 144 of the electrically insulating layer 14 which covers the semiconductor body 9.
The upper ends o~ the regions 141 and 11~3 are reduced in width and open out in a strip-shaped contact aperture 15, in which the layer 14 is etched away to the interface of the semiconductor boay 9. The lower ends o~ the regions 142 and 144, which are also reduced in width, open out in a correspondingly designed strip-shaped contact hole ~6. Above the contact holes 15 and 16 and the parts o~ the insulating layer 14 which directly surround these are placea strips 17 and 18 out of highly doped polycrystalline silicon, which are ad-~acent in the region of the contact holes 15 and lÇ directly to the inter~ace of the semiconductor body 9. Underneath the contact holes 15 and 16 there are located strip-shaped semiconductor regions, which are doped opposite to 9, which regions are indicatea hatched in Figure 3. For purposes of a simple representation, in Figure 3, their lateral boundaries coincide with the lim its of the contact holes 15 and 16.
~ etween the line structures 15, 17, and 16, 18, which serve as bit lines, and which are designed according to the Figures 1 and 2, a wide coat-ing 19 is applied upon the insulating layer 14, which consists of highly doped polycrystalline silicon. Within the individual gate o~ide regions 141 through 144, this in each case defines memory electrodes which are components of memory capacitors. One of the memory capacitors is designated wit,h the numeral 20 in Figure 3, and is represented hatched. ~ re~ion 21 nelgh~oring the capacitor 20~ which region 21 is also hatched in Figure 3, represents a 9 5 ~
transfer channel, via which charge carrieru proceed from the line structure 16, lô which serves as a bit line into the capacitor 20, and the reverse.
The transfer channel is covered by a transfer gate which consists of a fur-ther electrically conducting coating which is applied insulated with respect to the strips 17, 18 and the coating 19, which coating also is ~ormed out of highly doped polycrystalline silicon. For a better overvie~7, this coating is only represented for the memory cells 10 and 11 and is characterized in its lateral dimensions by means of the dot and dash line 22. Of the coating 22, in each case only those parts function as transfer gate electrodes which lie above the zones of the individual memory cells which correspond to the sur-face 21. ~he transfer gate electrodes which are associated with the memory cells 10 and 11 are selected via a word line 23, which is placed over an in-sulating layer which covers the coating 22 and which contacts the coating 22 by means of a contact hole 24 which is provided in this insulating layer.
~he bit lines 15, 17 and 16, 18 are connected via connection lines with read-and regenerating amplifiers 25 and 26, which serve for the reading out and regeneration of the information contained in the memory cells as well as which serve for the reading in again of the regenerated information. For ~he reading in of information, otherwise, further leads 27 and 28 of the bit lines 15, 17 and 16, 18 serve.
The coating 19 is finally connected via a lead 29 to a predeter-mined potential which permits space charge regions to arise under the regions 141 through 144, into which space charge regions, in the conducting state of the associated transfer channels in each case~ charge carriers which stem from the bit line penetrate, in a manner which is essentially known, so that inversion surface barrieræ form. Because of the low re~iutance of t~e ~it line structures 17 and 189 the transit time of the electric signals which represent the information from the individual memory cells 10 through 13 to 1 9~ 8 , ..
the reading and regenerating amplifier 25S or respectively~ 26 i8 small that in relationship to other processes which are relevant for the access time of a memory~ it is negligible. The transfer gate electrodes which consist of the parts of the coating 22 which are loc ted over the reeions 21 of the in-dividual regions 141 through 144 fill the space between the strips 17 and 18 on the one side and the border zones of the coating 19 on the other side such that they axe self-adJusting with respect to these parts. Therefore, between the transfer gate electrodes and the parts 17, 18 and 19, no fissures can arise, the siæe of which could be influenced by the precision oP adjustment of masks.
In the manufacture of a low resistance line according to the Fig-ures 1 and 2, one proceeds by covering a doped semiconductor body 1 at an interface with an electrically insulating layer 2. This layer 2 is provided with a strip shaped contact hole 3, in the region of which the material of the layer is removed up to the interface of the semiconductor body. FO11O~J-ing this, a coating of polycrystalline silicon is applied on the whole sur-face, which coating is ad~acent to the interface of the semiconductor body 1 within the contact hole 3. In a following doping process, as by a diffusion or implantation of doping substances, the necessary doping of the polycrys-talline coating is set. Simultaneously, however, the doping materials whichare used proceed through the coating in the region of the contact hole 3 into a zone of the semiconductor boay which is hereby redoped, so that a region 5 which is oppositely doped arises, which region proceeds from the contact sur-~ace of the polycrystalline coating and of the semiconductor body 1. Final-ly, by means of a photolithographic step which is known, the strip 4 ~Figure 1) is formed by means of etching away of the unnecessary parts of the coat-ing. With the increasing of the quantity of doping substances which pene~
trate into the region 5, its lower boundaxy is pushed rox~ard lnto the lnte-3,~ 8 rior of the semiconductor body 1, so that the~ region 5 obtains a larger cross section and thus has a lower re~istance. In the case of this method of pro-duction, it is a great advantage that the aoping of the polycrystalline coat~
ing can be dimensioned so large without difficulties that the zone 5 becomes su~ficiently low in resistance. Other reaoping regions of the semiconductor body 1 are not generated uith this doping process, so that it does not need to be broken off because o-f possible smaller dimensions which are desired for other redoping regions.
The semiconductor memory which is represented in Figure 3 is made essentially in the followine manner: The doped simiconductor body 9 is first provided on an interface with an electrically insulating layer 14, which dis-plays thin layer regions 141 through 141~, whereas outside of the same, it is designed as a thick oxide layer. Strip shaped contact holes 15 and 16 are provided in the layer 14. Following this, a coating out of polycrystalline silicon is applied which in particular extends over the whole surface, which coating is directly ad~acent to the interface of the semiconductor body 1~
insiae of the contact holes 15 and 16. In a following doping process, dif-fusion or implantation of doping substances, the necessary doping of the polycrystalline coating is set. Simultaneously, however, doping substances proceed into the region of the contact holes 15 and 16 through the coating into zones of the semiconductor body 9, which are thereby redoped. In this manner, underneath the contact holes 15 and lS, semiconductor regions arise which are doped oppositely to the body 9, which regions display a large cross section in the case of correspondingly stronger doping of the coating and are therefore of low resistance. Photolithographic steps follow, with which both the strips 17 and lo as well as the coating 19 which forms the memory elec-trodes are formed by means of removal of the unnecessary parts of the coat-ing. ~he structure which is obtained up till now is, following this, covered ~ 6 -1 ~ 5 8 Nith a further electrically insulating layer, fvr example, out of SiO2, over which a further coating out o~ polycrystalline silicon is applied especially over the whole surface. Out of the latter, after a preceding doping7 by means of further photolithographic steps, the gate structures are formed Nhich are characterized individually in Figure 3 with 22~ which gate struc-ture fit in self-adjustingly between the border zones Or the parts 17, 18 and 19 and which cover these over at least on the boundary side. An insulat-ing layer which is additionally applied~ which covers the structures 22, is provided with contact holes 24, in which word lines 23 which are placed over them, ~or example, out of aluminum, contact the structures 22. Finally, the strips 17, 18 and 19 are provided with connection lines.
It will be apparent to those skilled in the art that many modifica-tions and variations may be effected without departing from the spirit and scope of the novel concepts of the present invention.
Such lines are used, for example, as bit lines for semiconductor memories. The problem occurs that bit lines of memories with rather large memory capacities in general are so long that as a result of the line resistance of approximately 20 to 30 Ohms/square and the line capacitance during read-in and read-out of the information which is to be stored, delay times must be taken into ac¢ount which also determine the access time of the memory.
BRIEF SUM~ARY 0~ THE INVENTION
The invention is based upon the problem of providing a line having extremely low ohmic resistance. This is attained according to the present invention by means of the measures hereinafter described.
The advantage which was aimed for with the invention especially consists in that the resistance of the double line structure which is formed out of the oppositely doped region and the contacting strip is significantly smaller than the customary diffused lines. A further design of the concept of the invention, in the case of which a transfer gate is arranged next to the low resistance line, which transfer gate is self-adjusting in its lateral position with respect to the line edge.
Thus, in accordance with one broad aspect of the invention, there is provided a low resistance line comprising a strip-shaped region which is provided on the interface of a doped semiconductor body, the strip-shaped region being doped opposite to the doped semiconductor body, characterized in that above said region, a strip of highly doped polycrystalline silicon, which con-tacts said region is located, in which said low resistance line comprises a bit line of a dynamic one-transistor memory cell, and characterized in that it is arranged in a predetermined spacing to a memory electrode which is formed out of highly doped polycrystalline sillcon, a transfer gate being provided whlch L~
1 61~
covers said region and said memory electrode at least on their boundary sides, and which is electrically insulated against the same and against said interface of said semiconductor body.
In accordance with another broad aspect of the invention there is provided an integrated circuit semiconductor memory structure, comprising, a doped monocrystalline body of a first conductivity type, an insulating thick oxide layer covering said monocrystalline body and including a row of thin oxide regions~ first and second strip-shaped apertures extending through said oxide layer and spaced apart from one another, the thin oxide regions branching off alternately from said apertures, first and second bit lines each comprising contacting strips of doped polycrystalline material of an opposite, second conductivity filling respective strip-shaped apertures, and further comprising redoped regions in said body below said strips having said opposite, second conductivity, memory electrodes carried on said thin oxide regions, being form-ed by parts of a strip of doped polycrystalline material arranged between said bit lines on said insulating thick oxide layer, an insulating layer covering said bit lines and said memory electrodes, electrodes carried on said insulat~
ing layer and laterally extending alternately from the redoped region~of one of said ~it lines toward the other over said thin oxide regions, each of said electrodes including a portion adjacent the associated bit line defining a transfer electrode, a further insulating layer covering said electrodes, a plurality of third apertures extending through said further insulating layer to said electrodes, and word lines on said further insulating layer contacting said electrodes through said third apertures.
BRIEF DESCRIPTION OF THE DRAWINGS
.
The invention will be explained more closely in the following with the use of the drawing.
Figure 1 shows a view from above upon a low reslstance llne which -la-j, . . ~ ' ~ 3 6 ~ 8 is designed according to the invention, Figure 2 shows a cross section through the line according to Figure 1, and -lb-,, 1 9~5 ~
Fi.gure 3 sh~ws a view from above onto aeveral one-transistor mem~
ory cells ~hich are driven with lines aesigned according to the invention.
DESCRIPTIO~ OF THE PREFERRED EMBODIMENTS
In Figure 1, a highly doped monocrystalline semiconauctor body 1 is sho~n, which on that portion of its periphery which lies p~rallel to the drawing plane is covered with an electrically insulating layer 2. The semi-conductor body 1 consists by way of example of p-dopea silicon, while the in~
sulating layer preferably is maae of SiO2. A strip-shaped contact hole 3 is provided which is etched out of the layer 2. A strip ~, which is ~orrned on the insulating layer 2, is made of highly doped polycrystalline silicon, the lateral limits of which in Figure 1 are indicatea by a solid line, within the contact hole 3, i8 directly adjacent to the interface of the semiconductor body 1. Beginning ~rom the contacting surfaces of these two parts, a strip-shaped semiconductor region 5 is doped opposite to the semiconductor body 1, in the present case is n+ conducting, and extends parallel to the inter~ace, the lateral limits of which are also indicated. by means of a solid line.
Figure 2 shows a cross section along the line II-II of Figure 1.
Besides the semiconductor body 1, the layer 2 ~hich is designed as a thick field oxide layer, the strip 4 which contacts the interface o~ 1 and the re-doped semiconductor region 5, underneath the thick layer 2. A zone 6 whichis directly next to the interface of the semiconductor body 1 can be seen, which zone 6 is doped more strongly than the semiconductor body 1, and has the same kind of conductivity. Such a zone can be designated as field im-plantation or ~ield diffusion. It serves the purpose of de~initively limit-ing the redoped region 5 in a lateral direction.
Together with a contacting strip 4 out of highly doped polycrystal-line silicon, the redoped region 5 represents a double line structure, the resistance in Ohms o~ which is significantly umaller than that o~ a customary -- 2 ~
1 6~9~
diffusion line. The strip 4 i8 connected via a conne~tion line 7 (Figure 1) with a lead 8, in a practical manner.
In Figure 3, four one-transistor memory cells 10 through 13 are represented which are integrated upon a monocrystalline semiconductor body 9 and which are arranged in a row. Eac~l cell is associated with a somewhat rectangular shaped thin layer region (gate oxide region) 141 tbrough 144 of the electrically insulating layer 14 which covers the semiconductor body 9.
The upper ends o~ the regions 141 and 11~3 are reduced in width and open out in a strip-shaped contact aperture 15, in which the layer 14 is etched away to the interface of the semiconductor boay 9. The lower ends o~ the regions 142 and 144, which are also reduced in width, open out in a correspondingly designed strip-shaped contact hole ~6. Above the contact holes 15 and 16 and the parts o~ the insulating layer 14 which directly surround these are placea strips 17 and 18 out of highly doped polycrystalline silicon, which are ad-~acent in the region of the contact holes 15 and lÇ directly to the inter~ace of the semiconductor body 9. Underneath the contact holes 15 and 16 there are located strip-shaped semiconductor regions, which are doped opposite to 9, which regions are indicatea hatched in Figure 3. For purposes of a simple representation, in Figure 3, their lateral boundaries coincide with the lim its of the contact holes 15 and 16.
~ etween the line structures 15, 17, and 16, 18, which serve as bit lines, and which are designed according to the Figures 1 and 2, a wide coat-ing 19 is applied upon the insulating layer 14, which consists of highly doped polycrystalline silicon. Within the individual gate o~ide regions 141 through 144, this in each case defines memory electrodes which are components of memory capacitors. One of the memory capacitors is designated wit,h the numeral 20 in Figure 3, and is represented hatched. ~ re~ion 21 nelgh~oring the capacitor 20~ which region 21 is also hatched in Figure 3, represents a 9 5 ~
transfer channel, via which charge carrieru proceed from the line structure 16, lô which serves as a bit line into the capacitor 20, and the reverse.
The transfer channel is covered by a transfer gate which consists of a fur-ther electrically conducting coating which is applied insulated with respect to the strips 17, 18 and the coating 19, which coating also is ~ormed out of highly doped polycrystalline silicon. For a better overvie~7, this coating is only represented for the memory cells 10 and 11 and is characterized in its lateral dimensions by means of the dot and dash line 22. Of the coating 22, in each case only those parts function as transfer gate electrodes which lie above the zones of the individual memory cells which correspond to the sur-face 21. ~he transfer gate electrodes which are associated with the memory cells 10 and 11 are selected via a word line 23, which is placed over an in-sulating layer which covers the coating 22 and which contacts the coating 22 by means of a contact hole 24 which is provided in this insulating layer.
~he bit lines 15, 17 and 16, 18 are connected via connection lines with read-and regenerating amplifiers 25 and 26, which serve for the reading out and regeneration of the information contained in the memory cells as well as which serve for the reading in again of the regenerated information. For ~he reading in of information, otherwise, further leads 27 and 28 of the bit lines 15, 17 and 16, 18 serve.
The coating 19 is finally connected via a lead 29 to a predeter-mined potential which permits space charge regions to arise under the regions 141 through 144, into which space charge regions, in the conducting state of the associated transfer channels in each case~ charge carriers which stem from the bit line penetrate, in a manner which is essentially known, so that inversion surface barrieræ form. Because of the low re~iutance of t~e ~it line structures 17 and 189 the transit time of the electric signals which represent the information from the individual memory cells 10 through 13 to 1 9~ 8 , ..
the reading and regenerating amplifier 25S or respectively~ 26 i8 small that in relationship to other processes which are relevant for the access time of a memory~ it is negligible. The transfer gate electrodes which consist of the parts of the coating 22 which are loc ted over the reeions 21 of the in-dividual regions 141 through 144 fill the space between the strips 17 and 18 on the one side and the border zones of the coating 19 on the other side such that they axe self-adJusting with respect to these parts. Therefore, between the transfer gate electrodes and the parts 17, 18 and 19, no fissures can arise, the siæe of which could be influenced by the precision oP adjustment of masks.
In the manufacture of a low resistance line according to the Fig-ures 1 and 2, one proceeds by covering a doped semiconductor body 1 at an interface with an electrically insulating layer 2. This layer 2 is provided with a strip shaped contact hole 3, in the region of which the material of the layer is removed up to the interface of the semiconductor body. FO11O~J-ing this, a coating of polycrystalline silicon is applied on the whole sur-face, which coating is ad~acent to the interface of the semiconductor body 1 within the contact hole 3. In a following doping process, as by a diffusion or implantation of doping substances, the necessary doping of the polycrys-talline coating is set. Simultaneously, however, the doping materials whichare used proceed through the coating in the region of the contact hole 3 into a zone of the semiconductor boay which is hereby redoped, so that a region 5 which is oppositely doped arises, which region proceeds from the contact sur-~ace of the polycrystalline coating and of the semiconductor body 1. Final-ly, by means of a photolithographic step which is known, the strip 4 ~Figure 1) is formed by means of etching away of the unnecessary parts of the coat-ing. With the increasing of the quantity of doping substances which pene~
trate into the region 5, its lower boundaxy is pushed rox~ard lnto the lnte-3,~ 8 rior of the semiconductor body 1, so that the~ region 5 obtains a larger cross section and thus has a lower re~istance. In the case of this method of pro-duction, it is a great advantage that the aoping of the polycrystalline coat~
ing can be dimensioned so large without difficulties that the zone 5 becomes su~ficiently low in resistance. Other reaoping regions of the semiconductor body 1 are not generated uith this doping process, so that it does not need to be broken off because o-f possible smaller dimensions which are desired for other redoping regions.
The semiconductor memory which is represented in Figure 3 is made essentially in the followine manner: The doped simiconductor body 9 is first provided on an interface with an electrically insulating layer 14, which dis-plays thin layer regions 141 through 141~, whereas outside of the same, it is designed as a thick oxide layer. Strip shaped contact holes 15 and 16 are provided in the layer 14. Following this, a coating out of polycrystalline silicon is applied which in particular extends over the whole surface, which coating is directly ad~acent to the interface of the semiconductor body 1~
insiae of the contact holes 15 and 16. In a following doping process, dif-fusion or implantation of doping substances, the necessary doping of the polycrystalline coating is set. Simultaneously, however, doping substances proceed into the region of the contact holes 15 and 16 through the coating into zones of the semiconductor body 9, which are thereby redoped. In this manner, underneath the contact holes 15 and lS, semiconductor regions arise which are doped oppositely to the body 9, which regions display a large cross section in the case of correspondingly stronger doping of the coating and are therefore of low resistance. Photolithographic steps follow, with which both the strips 17 and lo as well as the coating 19 which forms the memory elec-trodes are formed by means of removal of the unnecessary parts of the coat-ing. ~he structure which is obtained up till now is, following this, covered ~ 6 -1 ~ 5 8 Nith a further electrically insulating layer, fvr example, out of SiO2, over which a further coating out o~ polycrystalline silicon is applied especially over the whole surface. Out of the latter, after a preceding doping7 by means of further photolithographic steps, the gate structures are formed Nhich are characterized individually in Figure 3 with 22~ which gate struc-ture fit in self-adjustingly between the border zones Or the parts 17, 18 and 19 and which cover these over at least on the boundary side. An insulat-ing layer which is additionally applied~ which covers the structures 22, is provided with contact holes 24, in which word lines 23 which are placed over them, ~or example, out of aluminum, contact the structures 22. Finally, the strips 17, 18 and 19 are provided with connection lines.
It will be apparent to those skilled in the art that many modifica-tions and variations may be effected without departing from the spirit and scope of the novel concepts of the present invention.
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A low resistance line comprising a strip-shaped region which is provided on the interface of a doped semiconductor body, the strip-shaped reg-ion being doped opposite to the doped semiconductor body, characterized in that above said region, a strip of highly doped polycrystalline silicon, which con-tacts said region is located, in which said low resistance line comprises a bit line of a dynamic one-transistor memory cell, and characterized in that it is arranged in a predetermined spacing to a memory electrode which is formed out of highly doped polycrystalline silicon, a transfer gate being provided which covers said region and said memory electrode at least on their boundary sides, and which is electrically insulated against the same and against said interface of said semiconductor body.
2. An integrated circuit semiconductor memory structure, comprising, a doped monocrystalline body of a first conductivity type, an insulating thick oxide layer covering said monocrystalline body and including a row of thin oxide regions, first and second strip-shaped apertures extending through said oxide layer and spaced apart from one another, the thin oxide regions branching off alternately from said apertures, first and second bit lines each comprising contacting strips of doped polycrystalline material of an opposite, second con-ductivity filling respective strip-shaped apertures, and further comprising redoped regions in said body below said strips having said opposite, second conductivity, memory electrodes carried on said thin oxide regions, being form-ed by parts of a strip of doped polycrystalline material arranged between said bit lines on said insulating thick oxide layer, an insulating layer covering said bit lines and said memory electrodes, electrodes carried on said insulat-ing layer and laterally extending alternately from the redoped region of one of said bit lines toward the other over said thin oxide regions, each of said electrodes including a portion adjacent the associated bit line defining a transfer electrode, a further insulating layer covering said electrodes, a plurality of third apertures extending through said further insulating layer to said electrodes, and word lines on said further insulating layer contacting said electrodes through said third apertures.
3. Method for the production of an integrated circuit semiconductor memory structure of the type set forth in claim 1 in which a doped semiconduct-or body is covered on an interface with an electrically insulating layer, said electrically insulating layer being subdivided into a thin layer region and a thick layer region, it being further provided with a strip-shaped contact hole, and a coating out of polycrystalline silicon being applied on said electrically insulating layer, said coating being next subjected to a doping process in which, in the region of said contact hole, doping substances penetrate through said coating into said semiconductor body and form a redoped region which is doped opposite to said semiconductor body, in which by means of photolitho-graphic steps, out of said coating on one side, a contacting strip is formed and on the other side above a part of said thin layer region a memory electrode is formed, in which a further electrically insulating layer is applied on the whole surface and, upon this, a further coating of electrically conductive material is applied, and out of this, by means of further photolithographic steps, a transfer gate is formed which covers the space between said memory electrode and said redoped region and additionally covers the memory electrode and the redoped region at least on their boundary sides, and the transfer gate, memory electrode and bit line are connected with connection lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792912858 DE2912858A1 (en) | 1979-03-30 | 1979-03-30 | LOW RESISTANT PIPE |
| DEP2912858.3 | 1979-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161958A true CA1161958A (en) | 1984-02-07 |
Family
ID=6067014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000348649A Expired CA1161958A (en) | 1979-03-30 | 1980-03-28 | Low resistance line |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0023241B1 (en) |
| JP (1) | JPS5664451A (en) |
| CA (1) | CA1161958A (en) |
| DE (1) | DE2912858A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126969A (en) * | 1980-03-11 | 1981-10-05 | Toshiba Corp | Integrated circuit device |
| JP2765583B2 (en) * | 1988-10-20 | 1998-06-18 | 株式会社リコー | Semiconductor memory device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE7137775U (en) * | 1970-10-06 | 1972-01-05 | Motorola | SEMI-CONDUCTOR ARRANGEMENT |
| GB1374009A (en) * | 1971-08-09 | 1974-11-13 | Ibm | Information storage |
| US4060796A (en) * | 1975-04-11 | 1977-11-29 | Fujitsu Limited | Semiconductor memory device |
| DE2543628C2 (en) * | 1975-09-30 | 1987-05-07 | Siemens AG, 1000 Berlin und 8000 München | Semiconductor component for storing information in the form of electrical charges, method for its operation and information storage with such semiconductor components |
| JPS52154377A (en) * | 1976-06-18 | 1977-12-22 | Hitachi Ltd | Forming method for contact parts in part of shallow diffused layer |
| FR2380620A1 (en) * | 1977-02-09 | 1978-09-08 | American Micro Syst | Programmable fixed value store with semiconductor substrate - has spaced regions diffused into semiconductor layer and gates extending down into common source region (NL 8.11.77) |
-
1979
- 1979-03-30 DE DE19792912858 patent/DE2912858A1/en active Granted
-
1980
- 1980-03-19 EP EP80101446A patent/EP0023241B1/en not_active Expired
- 1980-03-27 JP JP3962280A patent/JPS5664451A/en active Pending
- 1980-03-28 CA CA000348649A patent/CA1161958A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2912858A1 (en) | 1980-10-09 |
| JPS5664451A (en) | 1981-06-01 |
| EP0023241A2 (en) | 1981-02-04 |
| EP0023241B1 (en) | 1988-07-13 |
| DE2912858C2 (en) | 1987-08-27 |
| EP0023241A3 (en) | 1983-08-24 |
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