CA1115426A - U-groove mos device - Google Patents

Abstract

U-MOS SEMICONDUCTOR DEVICE

Abstract of the Disclosure A semiconductor device comprised of a plurality of U-MOS elements, each including a narrow, elongated recess having a U-shaped cross-section and formed by an anisotropic etchant in a silicon substrate material having a <110> crystalline plane surface and two <111>
planes perpendicular to the surface. Drain regions for each element are formed in the surface of an epitaxial layer extending over the substrate material which has the same conductivity as the drain regions and provides a common source for all U-MOS elements. Between the epitaxial layer and the substrate is a moderately doped intermediate layer having the opposite conductivity from and providing the effective device channel between the drain and source regions.
The U-MOS elements have an unusual and improved current carry-ing capacity and increased speed over prior art devices, as well as providing a higher density of elements per unit of chip area.

Description

i4;~6 3 Background of the Invention 4 This invention relates to semiconductor devices 5 and more particularly to those utilizing etched grooves ~ or recesses formed in crystalline semiconductor material.
7 As described in U.S. Letters Patent No. 3,975,221, 8 relatively low capacitance MOS (metal-oxide-silicon~ tran-~ sistors may be formed in conjunction with "V" shaped grooves 10 or recesses provided within the surface of silicon material.
11 Although the above noted patent covers V-groove MOS tran-12 sistors as logic devices, the application of V-MOS technology 13 to high current switching as well as audio and R.F. communi-14 cations has also been suggested. However, in order to 15 provide the necessary current capacity required for many 16 applications, a large number of elements on a semiconductor 17 chip are required. The use of V-MOS elements provided some 18 advantages over lateral or planar MOS elements by reducing 19 the area required, but the V-MOS devices previously devised 20 did not fully solve the problem for power devices.
21 With V-MOS devices, the V-grooves or recesses are ~2 formed by etching the crystalline silicon material along 23 its <111~ planes. For such crystalline material that is 24 sliced in wafer form so that its <100> plane is its hori-25 zontal surface, the <111> planes are oriented at an angle 26 of 54.74 with respect to the horizontal <100> pl~ne. Thus, 27 an anisotropic etchant will produce the desired "V" shaped 28 grooves along <111> planes wherever applied.
29 It is also know that when a silicon wafer is 30 sliced so that its <110~ plane is its horizontal surface,

-2-111S~6 1 four of its <lll> planes are vertical .o the ~110> plane 2 surface, and an anisotropic etchant ~ill produce "U"

3 shaped grooves ox recesses within the silicon material.

4 (See "On Etching Very Narrow Grooves in Silicon", Applied

5 Physics Letter, Vol. 26, Nos. 4, February 15, 1975). Such

6 "U" shaped grooves have parallel and vertical side walls

7 because the etchant does not act on the <111> planes which

8 are perpendicular to the C110> plane horizontal surface.
g An advantage of the parallel and vertical side 10 walls is that the depth of the U-shaped grooves is not 11 proportional to their width. This is important where it is 12 necessary for the groove to extend completely through an 13 epitaxial layer on the device substrate which serves as a 14 common source region. However, one serious disadvantage of 15 a U-shaped groove etched on <llo? surface plane material 16 is that during the etching process the silicon material 17 also etches along various other planes that create 18 irregular surface patterns at the bottom and ends of each 19 recess to its parallel, vertical walls. The present 20 invention overcomes these disadvantages in a U-MOS high ~1 current device.

23 Summary of the Invention 24 The features and advantages of the invention ~5 are provided in one embodiment wherein a semiconductor 26 device comprises a silicon substrate of a first conduc-27 tivity type material covered with an epitax,ial layer of 28 sufficient thickness (e.g. 3.5 microns). Transistor 29 elements of the device are formed in conjunction with 3~ elongated, narrow recesses or grooves that have a ' 1 U-shaped cross-section and extend through the epitaxial layer 2 :into the device substrate which forms a common source 3 region for the MOS device. A series of such elements 4 are arranged in a closely spaced apart, parallel array 5 on the semiconductor chip. A thin layer of silicon 6 dioxide covers the vertical and bottom walls of each 7 recess and is filled with conductive polycrystalline 8 silicon which forms the gate for the device. The gate g layer common to all elements extends to one side of the 10 array of elements. The conductive material of this gate 11 layer fills essentially the entire void of each recess 12 including areas normally occurring at opposite ends of the 13 recess. At the upper end of each recess and extending 14 between adjacent recesses are drain regions of the same 15 conductivity type material as the substrate material.
16 These drain regions extend via a common conductive layer to 17 an elongated contact pad spaced from the ends of the 18 recesses. Covering the drain elements around the upper end 19 Of each recess is a thicker layer of insulating oxide 20 material. ~ecause the depth of each U-MOS recess is not re-21 lated to the surface area, the array of U-MOS transistors 22 can be made with a relatively thick epitaxial layer that may 23 be needed to optimize device performance and also production 24 yield. Thus, a relatively large current carrying device 25 utilizing a plurality of such U-MOS transistors requires 26 substantially less chip area than prior devices including 27 V-MOS devices. This and other advantages of the present 28 invention are also available for semiconductor logic and 29 memory devices comprised of such U-MOS transistors.

It is therefore one object of the present ~llS~

. . . ~

1 invention to provide an improved semiconductor device 2 having a relatively high current capacity per unit area.
3 Another obiect of the present invention is to 4 p:rovide a semiconductor device utilizing one mor ~ore 5 U-shaped recesses or grooves forming one or more MOS
6 transistor elements of the device.
7 Another object of the invention is to provide a 8 high current semiconductor device utilizing a minimum

9 amount of chip surface area.
Another object of the invention is to provide 11 a high current semiconductor device utilizing a plurality 12 of U-shaped grooves whose depth is independent of width 13 and which therefore can be arranged as an array of 14 parallel and closely spaced elements.
Another object of the invention is to provide 16 a semiconductor device comprised of U-MOS elements that 17 require less chip area and yet operate at a greater 18 speed than prior art elements.
19 Yet another object of the invention is to 20 provide a high current semiconductor device comprised 21 of a plurality of elongated U-MOS transistor elements 22 axranged in a parallel, closely spaced apart array 23 that extent into a common source and with drain regions 24 connected to a common contact area.
Another object of the invention is to provide 26 an improved method for manufacturing a high current 27 capacity U-MOS semiconductor device.
28 Other objects, advantages and features of the 29 invention will become apparent from the following detailed 30 description presented in conjunction with the drawing.

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1 Brief Description of the Drawing 2 Fig. l is a plan view of a silicon wafer having 3 its upper surface in a <100~ crystal plane and showing a 4 single etched V-groove in its surface;
Fig. 2 is a plan view of a silicon wafer having 6 its upper surface in a <110> crystal plane and showing a 7 single etched U-groove in its surface;
8 Figs. 3a, 3b, 4a, 4b, 5a and 5b are plan and 9 perspective dlagrammatic views showing the progressive

10 formation of a U-shaped groove in <110> plane silicon;

11 Fig. 6 is a fragmentary plan view showing a

12 V-MOS power device;

13 Fig. 7 is an enlarged view in section taken

14 along line 7-7 of Fig. 6;
Fig. 8 is a fragmentary plan view showing a 16 U-MOS power device according to~the present invention;
17 Fig. 9 is an enlarged view in section taken 18 along line 9-9 of Fig. 8;
19 Fig. 10 is graph showing dimensional relationships 20 of useful V-MOS and U-MOS devices; and 21 Fig. ll is a representative graph showing drain 22 current vs. drain to source voltage for a typical U-MOS
23 device.

.... ....

1 Detailed Description of Embodiments _ _ _ _ 2 With reference to the drawing, Figs. 1 and 2 3 are presented to illustrate the characteristics of two 4 different forms of crystalline silicon material, only one form of which is utilized by the present invention. Fig.
6 1 shows a conventional silicon wafer 20 whose index flat 7 22 is parallel to the <110~ crystal plane and whose 8 horizontal surface is parallel to the < 100~ crystal plane.
g In such a wafer the <111> crystal planes extend inwardly 10 from the wafer surface at an angle. Therefore, when an 11 anisotropic etchant is used to form recesses 24 on the 12 wafer surface (as indicated by the superimposed recess 13 diagrams), these recesses have a square of rectangular plan-14 form surface shape with side and end edges parallel and

15 perpendicular to the <111~ index flat and a V-shaped verti-~6 cal cross section. In contrast, Fig. 2 shows a silicon wafer 17 26 whose index flat 28 is parallel to one of the ~111~
18 crystal planes of the wafer which is perpendicular to the 19 wafer's ~1107 crystal plane surface. Another such crystal 20 plane, designated <111~ , is also perpendicular to the wafer 21 surface but is oriented at an angle 0 relative to the other 22 111 plane and the parallel index flat. The angle 0 =
23 cos 1 1 = 70.53, which is derived from the geometry of the 24 silicon crystalline structure. Thus, in this latter wafer an 25 anisotropic etchant will form a recess 30 on the wafer surface 26 (as indicated by the superimposed recess diagram), having a 27 general parallelogram shape with opposite side walls 32 para-28 llel to the <1117 index plane, and/or (depending on the mask 29 orientation it may also form a recess 30a with side walls 32a 30 parallel to a <lll>'crystal plane.

1 The end walls of the recesses 30 and 30a are 2 comprised of intersecting surfaces that are parallel to 3 other <lll> planes of the crystalline structure. However, 4 for most of its length each recess 30 or 30a has a U-shaped 5 vertical cross section with a constant width which is 6 independent of its depth within the wafer.
7 The progressive formation of the recess 30 8 using an anisotropic etchant on a silicon wafer with a g crystal structure as shown in Fig. 2, is illustrated 10 diagrammatically in Figs. 3a - 5_. To commence the 11 etching process an oxide mask is used with a rectangular 12 shaped opening 34, as shown in Fig. 3a, with two parallel 13 sides 36 also being pzrallel to the ~111> direction or the 14 index flat 28 of the wafer. This opening is shown in 15 perspective in Fig. 3b with dotted lines indicating the

16 side planes 36 which are parallel to the index flat and

17 transverse and skewed end planes 38 parallel to other

18 ~lll> planes of the crystal.

19 Figs. 4a and 4b show the recess 30 as it appears

20 further along in the etching processl commencing to form

21 along six walls which are parallel to the various <111>

22 crystal planes. Two of these walls are the opposite side

23 walls 36 which are perpendicular to the wafer's <110>

24 index plane surface. End walls formed by the <111>

25 planes 38 at the ends of the recess are also perpendicular

26 to the wafer surface. Also formed parallel to fifth and

27 sixth <lll> planes of the crystal are two internal sloped

28 end surfaces 40 and 42. In Figs. 4a and 4b, these end

29 surfaces, which sloped downwardly from surface edges 44, have

30 terminated at opposite ends of a horizontal bottom 46 of the 1 recess.
2 As shown in Figs. 5a and 5_, when the etching 3 process is allowed to continue, it reaches a self stopping 4 depth when the sloping end surfaces 40 and 42 eliminate S the horizontal bottom and ultimately meet at a common line 6 48 of maximum depth. Along the upper edges of the recess 7 the surfaces are intersected by the planes 36 and by the 8 additional <lll~ end planes 38 which are further skewed to 9 the planes 36.
It is apparent from the foregoing analysis of the 11 anisotropic etching process on silicon material oriented with 12 a ~110> plane index surface that if the recess is made 13 quite long compared with its depth, its sloped end planes 14 40 and 42 will terminate at the far ends of an elongated 15 horizontal bottom 46. In such a recess the irregular 16 shaped ends of the recess become insignificant electrically 17 and essentially the entire recess is a narrow slot with 18 parallel opposite walls, a flat bottom and a U-shaped 19 cross section. As described hereafter, such elongated 20 recesses may be utilized to form power type U-MOS devices 21 and also logic type U-MOS devices in accordance with the 22 principles of the present invention.
23 Turning to Fig. 6 a portion of a semiconductor 24 device 50 is shown which is particularly adapted for large 25 current carrying applications as in high load switching 26 circuits. In general, this device comprises a series of 27 V-groove MOS transistors connected in parallel by a 28 common gate electrode 52 and a common drain electrode 54.
29 As shown in the enlarged cross section view of Fig. 7, 30 the device is formed on a substrate 56 of heavily doped , fi _ _ _ ., . . , . . . , . . _ 1 N-type conductivity material (e.g., N-doped with antimony 2 in the range of 2X10l~ to lx10l9 atoms per cubic cm 3 whose horizontal surface is parallel to the ~110~ crystal 4 plane and on which is an epitaxial layer 58 of lightly doped 5 P-type of Pi type material. Between the epitaxial layer 6 and the substrate is an intermediate layer 60 of more 7 heavily P-doped material that is rormed by the outdiffusion 8 of P-type material from the substrate. Etched within the 9 surface of the device 50 are a series of V-shaped grooves 10 62 which are formed when an anisotropic etchant is used lL on ~ 100~ surface plane silicon material. The V-grooves 12 are spaced apart by a minimum design distance (e.g. 3 micron) 13 and they each extend through the epitaxial layer 58, the inter-1~ mediate layer 60 and into the substrate 56. The substrate 15 serves as a common source to all of the V-groove MOS
16 transistors. Each of the etched V-grooves is elongated so 17 that its length is several times its width and the walls 18 of each groove are provided with a thin gate oxide layer 64 19 of silicon dioxide. A gate electrode 66 which may be a 20 suitable metal or polycrystalline silicon covers the thin 21 oxide layer 64 in each recess and forms the common electrode 22 52 extending essentially perpendicular to each V-groove ele-23 ment. Between the parallel V-groove elements are diffused N-type 24 drain re~ions 68 having essentially the same characteristics 25 as the substrate source material. Covering each of these 26 drain regions is an insulative oxide layer 70.
27 A semiconductor device 72 embodying the principles 28 of the present invention is shown in Figs. 8 and 9.
29 Here, the device comprises a substrate 74 of N-type 30 silicon material formed with its surface in the ~110 4;~:fi 1 crystal as shown in Fig. 2. It also has an epitaxial 2 layer 76 and an intermediate layer 78 having the same 3 characteristics as those elements in the V-groove device 4 5t). Within the surface of the device 72 are a series of 5 narrow, elongated etched U-shaped grooves or recesses 6 30 of the type that are formed as shown in Figs. 3a - 5b.
7 As shown in Fig. 9, these recesses have vertical, paral-8 lel sidewalls and they extend through the epitaxial layer 9 76, the intermediate layer 78 and into the substrate 74.
10 At the opposite ends of each recess 30 the etching process 11 creates the intersecting and sloped surfaces 40 and 42 12 that follow the tilted ~111> crystal planes. However, 13 because the recesses are relatively long and narrow these 14 irregular surfaces at each end are inconsequential to 15 the electrical functioning and fabrication of the device, 16 and the recesses are essentially uniform in their U-shaped 17 cross section with a flat bottom surface 46 throughout 18 their length.
19 Within each recess is a thin oxide layer 80 forming 20 a gate oxide. Covering this thin oxide layer and completely 21 filling each recess is a conductive material 82 such as a 22 suitable metal or preferably polycrystalline silicon that 23 provides the gate electrode for each U-MOS element. As in 24 the V-MOS device these gate electrodes for each of a series 25 of U-MOS elements forming the device 72 are connected as an 26 integral conductive element 84 that extends to one side of 27 the array of recesses 30. Between the U-shaped recesses are 28 diffused N~ drain regions 86 as in the V-MOS device and 29 these regions are also covered with an insulative oxide 30 layer 88. The drain regions extend beyond the ends of the 4~:fi 1 recesses and are connected together by a common contact 2 pad 90 on the surface of the device.
3 Significant advantages of the U-MOS device as 4 compared with the V-MOS device may be readily seen by the 5 following analysis. Assuming presently accepted design 6 rules in the semiconductor industry with respect to 7 limitations of photo lithography in device layout and 8 considering the necessity for both the V-grooves and g U-grooves to extend through the epitaxial layer into the 10 common source substrate, the minimum width of a V-MOS
lL recess must be five (5) microns. Now, since the opposite 12 sidewalls of each U-MOS element 30 are vertical and can 13 extend to any depth necessary to penetrate the epitaxial 14 layer 76, the width of such a U-MOS element can be one (1) 15 mieron. The lengths of both V-MOS and U-MOS elements would 16 be comparable as would the spacing between elements, e.g.
17 three (3) microns. Therefore, the total surface width 18 required for a V-MOS element would be eight (8) microns, g while the total width for a U-MOS element would be four 20 (4) microns. Thus, each V-MOS element requires twice 21 the area of a U-MOS element. Now, with regard to channel 22 length lL) assuming that the channel length (i.e., the 23 distance from the diffused drain region to the source 24 substrate) for the U-MOS element is one (1), it will be 25 readily seen that geometrically the channel length along 26 eaeh sloped sidewall of the V-MOS element is ~31 ~ .
27 In terms of channel conductance which is proportional to the 28 reciprocal of channel length ( ~ 1) and assuming that a 29 V-MOS element has a channel conductance of 1.0, a comparable 30 U-MOS element will have a channel conductance of 1.22. To ~ ;' ': , :

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1 provide a measure of device efficiency, one can determine 2 the amount of transistor area for a given conductance. If, 3 i~ the above example, the ~r-MOS device has an area per 4 conductance factor of 1.0, the U-MOS device will have the 5 same factor of 0.41. Thus, it is readily seen that the 6 U-MOS device will provide the same electrical performance 7 using only 41% of the area of a comparable V-MOS device.
8 Considering the area normally required for peripheral logic, g a power type chip of the type described could require 10 around 200 square mils when made in a V-MOS configuration, 11 whereas a chip with the equivalent number of U-MOS
12 transistors and with the same electrical capability would 13 require only 128 square mils. When this fact is applied 14 to the known statistical relationships of manufacturing ' 15 yield and chip area, the increased yield attainable with the 16 smaller sized chip becomes a significant advantage.
17 To provide the area advantage over V-MOS as described 18 above, the U-MOS device should have a minimum width between 19 its vertical, parallel side walls and this width is 20 ideally between 1 and 2 microns. Due to the crystalline 21 structure of silicon with a C110> crystal plane surface, 22 the U-groove will etch as shown in Figs. 3a - 5b and will 23 be self-stopping. Actual tests have shown that the self-24 stopping depth of the U-grooves is a function of both 25 width and length of the mask opening. The dimensional 26 relationship of U-groove width and length necessary to 27 obtain penetration of a uniform epitaxial layer(XE) of 2.4 28 micron thickness is shown in Fig. 10. From this it is 29 seen that for a practical U-MOS device the length of each 30 etched U-groove should be greater than 8 and at least .. ..

- :,:

1 around 10 microns (assuming a minimum width of around 1 2 micron), in order to obtain adequate penetration of an 3 epitaxial layer of around 2.4 microns. From the graph 4 of Fig. 10, it is also apparent that for any U-MOS device 5 greater than 8-10 microns in length, adequate penetration 6 of the epitaxial layer will be accomplished for any width 7 of U-groove, no matter how small. While maintaining the 8 minimum width of around 1 microns, the advantages of the 9 U-MOS increase as its length increases.
Another significant advantage of a U-MOS device 11 over a similarly sized V-MOS device is that it is inherently 12 faster in circuit operation. This is derived from the fact 13 that for two narrow, equally long and equally deep V-MOS
14 and U-MOS devices, the V-MOS gate capacitance Cg is ~
15 larger than the U-MOS gate capacitance, and the V-MOS "on"
16 resistance (RoN) which is proportional to the channel length 17 (L) is ~ / ~ larger than the U-MOS "on" resistance.
18 As is well known in the art, device speed is a function of 19 the time factor constant ~ , which is the product of its 20 "on" resistance RON and its gate capacitance (Cg). There-2~ fore, assuming a U-MOS device with these factors at one, a 22 V-MOS device would have a value of r= RON x Cg =
23 - x - = 1.5, or in other words, the U-MOS device will be ~ 2 24 approximately 1.5 times as fast as a similarly sized V-MOS
25 device.
26 The ON resistance factor may be illustrated by 27 reference to Fig. 11, which is an I-V characteristic 28 curve for a 1 micron width by 25 micron length U-MOS device.
29 On this curve are plotted drain current vs. drain to source 30 voltage for different gate voitages impressed on the device.

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. . _ _ . . . , _ _ . . . _ 1 The ON resistance which is the resistance that occurs 2 when the device turns "on" is essentially the initial slope 3 of each plot. Tests of actual devices as exemplified in 4 Fig. 11 have verified the fact that a U-MOS device having 5 the same channel width as a V-MOS will have a smaller 6 "ON" resistance (and therefore greater current capability) 7 by a factor of about '~.
8 In manufacturing the U-MOS 72, the method steps g used can be primarily those that have been heretofore 1~ applied generally in the fabrication of V-MOS devices. , 11 For example, the formation of the substrate epitaxial layer 12 and intermediate layer can be as described in U.S. Patent 13 No. 3,975,221 except that the substrate must be <110>
14 crystal plane material. When the U-MOS grooves are formed, 15 they are etched anisotropically through rectangular oxide 16 windows parallel to the Clll> or ~ ' planes as shown 17 in Figs. 3a - 5b and they are relatively long (greater 18 than 10 microns) compared with their width (one (1) micron).
19 The resulting U-shaped grooves will be generally parallelo-20 gram shaped with four vertical walls and two sloping end 21 walls. The thin gate oxide layer within the etched 22 U-grooves is formed using conventional masking and 23 deposition techniques, and the drain regions are preferably 24 formed by ion implantation. The gate electrodes, prefer-25 ably of polycrystalline silicon material are also formed 26 by deposition techniques and preferably fill each narrow 27 U-groove. The interconnecting conductors between elements 28 may be formed simultaneously from the same material or 29 from metal. With the U-grooves or recesses filled, a 30 metallized layer for interconnecting conductor portions ~ , :

Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A semiconductor device flow comprising:
a substrate of crystalline silicon material having its upper surface in a <110> crystal plane and a dopant concentration providing a source with a conductivity of the first type;
an epitaxial layer on said substrate having a dopant concentration providing a conductivity of the second type;
a relatively thin intermediate layer between said substrate and said epitaxial layer and having a conductivity of said second type but with a greater concentration;
a series of elongated, spaced-apart and parallel recesses extending from the surface of said device through said epitaxial and intermediate layers and into said substrate, each said recess having parallel opposite side-walls that are perpendicular to said <110> crystal plane of the surface of said device and form a U-shaped groove for substantially its entire length;
a thin oxide layer within each said recess;
relatively shallow drain regions of material having a conductivity of said first type located adjacent the upper ends of said sidewalls of each said recess;
a relatively thick layer of insulative oxide material extending over each said drain region;
a layer of conductive material covering said thin oxide layer within each recess;
conductive means extending between adjacent recesses over said insulative material and said drain regions to a first contact means;
means connecting said drain regions to a second contact means; and means providing a contact to said substrate source.

2. The semiconductor device as described in Claim 1 wherein said drain regions are joined together between adjacent recesses.

3. The semiconductor device as described in Claim 1 wherein said conductive means extending between adjacent recess is a continuation of said layer of material covering said thin oxide layer within each said recess.

4. The semiconductor device as described in Claim 1 wherein the length-to-width ratio for each said recess is greater than 10.

5. The semiconductor device as described in Claim 1 wherein the width of at least some of said recesses is between one and two microns and the length is greater than ten microns.

6. The semiconductor device as described in Claim 1 wherein said substrate and said drain regions have an N-type conductivity and said epitaxial layer has a lightly doped P-type conductivity.

7. The semiconductor device as described in Claim 1 wherein each said recess has four walls that are perpendicular to said surface of the device and two walls at opposite ends of each recess which slope inwardly from said surface.

8. The semiconductor device as described in Claim 1 wherein said layer of conductive material within each recess completely covers said thin oxide layer and fills the recess.

9. The semiconductor device as described in Claim 1 wherein said epitaxial layer is between 2 to 3 microns in thickness.