CA1152226A - Process for the manufacture of printed circuits - Google Patents

Process for the manufacture of printed circuits

Info

Publication number
CA1152226A
CA1152226A CA000357874A CA357874A CA1152226A CA 1152226 A CA1152226 A CA 1152226A CA 000357874 A CA000357874 A CA 000357874A CA 357874 A CA357874 A CA 357874A CA 1152226 A CA1152226 A CA 1152226A
Authority
CA
Canada
Prior art keywords
copper
process according
boreholes
bath
chemical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000357874A
Other languages
French (fr)
Inventor
Claus-Werner Ruff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bayer Pharma AG
Original Assignee
Schering AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schering AG filed Critical Schering AG
Application granted granted Critical
Publication of CA1152226A publication Critical patent/CA1152226A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/0542Continuous temporary metal layer over metal pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1423Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Abstract

ABSTRACT OF THE DISCLOSURE
The resent invention provides a process for the manufacture of printed circuits using copper-laminated substrate material which, after boring or punching, is brushed, degreased, etched slightly, activated and reduced, characterised in that the substrate material prepared in such a manner is printed with an etch resist which covers the desired series of conductors, whereupon first of all the copper lamination is etched away and then the etch resist is removed by means of a solvent to bare the conductors, then either the lacquer layer is first applied, leaving the boreholes and soldering eyes uncovered, and these are then, to produce a conductive connection between the conductors and boreholes, provided with a layer of copper by the action of leaving the boreholes and soldering eyes uncovered, and these are then, to produce a conductive connection between the conductors and boreholes, provided with a layer of copper by the action of a chemical copper bath, or the entire surface is first coated with a layer of copper by the action of a chemical copper bath, then the lacquer layer is applied, leaving the boreholes and soldering eyes uncovered.

Description

~ZZZ6 The present invention relates to a process for the manufacture of ~rinted circuits using copper-laminated substrate material which, after boring or punching, is brushed, degreased, etchea slightly, activated and reduced in a conventional manner.
Processes for the manufacture of printed circuits are known, but these have certain disadvantages. A disadvantage of the so-called subtractive technique is, for example, that large quantities of the lamination of the substrate material have to be removed once the conductive pattern has been applied.
At the same time, under-cutting of the series of conductors occurs with all the known impairments which, the narrower the conductive paths and the distances between them, are all the more serious and, as a percentage, increase more quickly. llhese phenomena therefore preclude further miniaturisation by the subtractive technique. A disadvantage of the so-called additive techni~ue is that the substrate material used must be coated with an adhesion-imparting agent. The adhesion-imparting agent is, after chemical dissolution and activation have been carried out, the base for the selectively applied, chemically deposited copper ~0 and, after the wet treatment, has distinctly poorer electrical characteristics as compared with epoxy resin, as a result of which, similarly, narrow limits are placed on the use of tllls tecllni~ue for ~ro~ucinc3 miniaturis~d ciraults.
A furtller disadvantac3e of these processes is that ~o apply the series of conductors and the conductive connection between them and the boreholes, considerable quantities of copper bath solution are required.
The present invention provides a process which, whilst avoiding the disadvantages of the known processes, reaches possible the manufacture of printed circuits with very fine conductor series on a very narrow area with optimal electrical chdracteristics using very small ~uantities of copper bath solution.

~52~26 In accordance with the present invention in a process of the type described above the substrate material prepared in such a manner is printed, preferably by the positive process, advantageously using an alkali-soluble silk-screen printing ink, with an etch resist which covers the desired series of conductors, whereupon first of all the copper lamination is etched away and then the etch resist is removed by means of a solvent to bare the conductors, then either first of all the lacquer layer is applied, leaving the boreholes and soldering eyes uncovered, and these are then, to produce a conductive connection between the conductors and boreholes, provided with a layer of copper by the action of a chemical copper bath and subsequently, if desired, covered with a lead/tin alloy, or first of all the entire surface is coated with a layer of copper by the action of a chemical copper bath, then the lacquer layer is applied, leaving the boreholes and soldering eyes uncovered, and these are subsequently, if desired, provided with a covering of lead/tin alloy.
In preferred embodiments of this process:
(a) the copper lamination is etched away by means of an acidic etchin~ solution, advantagoously an clCidiC a~noniurn persulphate solution, or an ~lkaline etching solution, advantageously an ammoniacal solution o~ sodium chl.orite;
(b) the etch resist is removed by means of a 3 to 5%
sodium hydroxide solution or an organic solvent, advantageously methylene chloride;
(c) the lacquer used is a solder-blocking lacquer;
(d) a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, as well as an alkali cyanide and optionally a selenium compound as stablilisers; and (e) a stabilised chemical copper bath is used;

1~2226 (f) the lead/tin alloy is applied in the form of a melt by the action of very hot air or by reductive deposition from a chemical tin bath.
The process according to the invention makes possible in a surprising manner, the manufacture of high-quality minia-turised circuits, especially by positive printing. The process produces fine conductors of a quality that can otherwise be obtained only by using photographic printing. The process furthermore has the great advantage that, starting from a cop-per-laminated substrate material, it is possible to produce the finest conductor paths in a width of less than 100 ~m with optimal insulation and surface resistance properties.
A further important advantage is the saving of chemical copper bath solution, which is of special economic significance.
Of outstanding commercial importance, furthermore, is that by contrast with the additive technique, it is possible to dispense with an adhesive-coated or nuclear-catalysed substrate material so that the high requirements of the adhesive coating and the oxidative decomposition of the adhesive layer by means of chromosulphuric acid are inapplicable. The process accord-ing to the invention thus has an especially low pollution ef~ec~.
~ suitable sub~trate material is, ~or example, phenol resin-bonded paper, epoxy resin paper, and especially glass-fibre-reinforced epoxy resin.
The present invention will be further illustrated, by way of the accompanying drawings, in which:
Fig. 1 is a flow diagram of a process for the manu-facture of printed circuits according to one embodiment of the present invention; and Fig. 2 is a flow diagram of a process for the manu-facture of printed circuits according to allother embodiment of , ;, ~52~Z6 the present lnvention.
The process according to the invention is carried out, for example, after boring or punching, by brushing the plates in the conventional manner followed by alkaline degreas-ing. The surface is then etched slightly about 5 m~, which can be effected by the action of approximately 10~ sodium per-sulphate solution at 28-32C. After pickling, for example, with 10% sulphuric acid, the surface is then activated by means of an activator, preferably an aqueous alkaline solution of a palladium - 3a -~;2226 complex, especially palladium sulphate with 2-aminopyridine, wherein attention is to be paid to a high covering density especially on the borehole walls so as to ensure activation even after the later etching operation. Reduction is then carried out by the action of a reducing agent, for example sodium diethylaminoborane, and the surface is after-treated in the usual manner.
The desired wiring pattern is then positively applied thereto in accordance with the invention by silk-screen or photographic printing, which is effected by means of an etch resist, advantageously an alkali-soluble silk-screen printing ink, which covers the conductors, after which first of all the copper lamination is etched away, which can be carried out by the action either of an acidic etching solution, for example an acidic ammonium persulphate solution, or of an alkaline etching solution, for example an ammoniacal sodium chlorite solution.
Subsequent thorough rinsing of the boreholes or punched holes must be carried out.
After removing the etch resist by means of a solvent, for example by means of a 3 to 5% sodium hydroxide solution, or an organic solvent, such as methylene chloride, according to one embodiment of the process in accordAnG~ with ~he invention, a lacquer layer is th~n appli~, leavin~ tlle borehoJ.cs un~ovcred, for which purpose a solder-blocking lac~uer is especially suitable, this being applied as a mask print. After customary alkaline degreasing, chemical deposition of metal into the boreholes is then carried out to a layer thickness o preferably 15 to 25 m~ . This is advantageously effected with a stabilised chemical copper bath preferably containing, as the essential constituents, a copper ~alt, a complex former, formaldehyde, as well as an alkali cyanide and optionally a selenium compound as stabilisers.

The final partial application of a lead/tin alloy, ^`` ~1~i;2226 advantageously in a hot air process by the action of very hot air, guarantees a purely eutectic solder which, even after accelerated ageing, is satisfactorily solderable.
In accordance with another embodiment of the process according to the invention, after removing the etch resist the entire surface is copper-plated by the action of the above-described chemical copper bath, then the solder~blocking lacquer is applied leaving the boreholes uncovered, and finally, if desired, the mentioned hot-air tinning is carried out.
A chemical copper bath of the above-described composition is excellently suitable for carrying out the process according to the invention. A suitable alkali cyanide is especially sodium cyanide in c~centrations of 15 to 30 mg/litre.
Suitable selenium compounds are the organic, inorganic, and organic/inorganic monoselenides and diselenides and, of these, especially alkali metal selenocyanates, such as potassium selenocyanate, which are used in concentrations of, preferably, 0.1 to 0.3 mg/litre of bath liquid.
The following Example serves to illustrate the invention.
EXAMPLE
A substrate of ~lass-Eibre-reinEorcod epoxy rcsin which is copper-laminated on both sides is bored in the usual manner, mechanically cleaned (burred), and degreased by means of al]cali at approximately 80C with a treatment time of about 7 minutes. The substrate is then etched slightly (approximately 5 m~) by the action of a 10~ sodium persulphate solution at a temperature of approximately 28 to 32C within a period of 3 minutes. The substrate is subsequently pickled with sulphuric acid with a content of 10% by weight at room temperature and then activated with an aqueous alkaline solution ofpalladiumsulphatein 2-aminopyridine, whereupon it is reduced using sodium diethyl-.~5Z~226 aminofurane as reducing agent, then rinsed and dried.
The conductive pattern is then printed positively bysilk-screen printing using an alkali-soluble silk-screen printing ink. The printing can alternatively be carried out by the photographic method, wherein advantageously an alkali-soluble liquid resist may be used. The copper is then etched away, which may be effected by the action of an acidic etching solution, such as an acidic ammonium persulphate solution, or an alkaline etching solution, such as an ammoniacal solution of sodium chlorite.
The removal of the silk-screen printing ink is then effected by treating with a solvent, such as a 3 to 5% sodium hydroxide solution or methylene chloride, after which the substrate is thoroughly rinsed and dried. A solder-blocking lacquer is then applied, followed by alkaline degreasing. The boreholes are subsequently copper-plated by means of a stabilised chemical copper bath of the following composition:
g/l of copper sulphate CuSO4 5H2O
g/l of ethylenediaminetetraacetic acid g/l of sodium hydroxide NaOH
0.025 g/l of sodium cyanide NaCN
0.001 g/l o ~otassium seJ.~noa~anate KSe~N
4 ml o formal~ehyde, 37%.
The copper deposition is effected at a temperature of 65C and a treatment time of 20 hours at an average deposition speed of 1.5 ~m/hour. If desired, a selective hot-air tinning (so-called HOT-~IR-LEVELLING process) can then finally ~e carried out.
Alternatively, the solder-blocking lacquer can first be applied after copper-plating, whereupon finally, if desired, selective hot-air tinning is carried out.
The result is series of conductors in a layer thick-ness of ~pproximately 30 ~m with electrical characteristicsof at least 1 . 1012Q.

Claims (18)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A process for the manufacture of printed circuits using copper-laminated substrate material which, after boring or punching, is brushed, degreased, etched slightly, activated and reduced, in which the substrate material prepared in such a manner is printed, with an etch resist which covers the de-sired series of conductors, whereupon first of all the copper lamination is etched away and then the etch resist is removed by means of a solvent to bare the conductors, then applying a lacquer layer to said substrate leaving the boreholes and solder-ing eyes uncovered and providing a layer of copper by the action of a chemical copper bath on said boreholes and soldering eyes to produce a conductive connection between the conductors and the boreholes.
2. A process according to claim 1, in which the lacquer layer is first applied, leaving the boreholes and soldering eyes uncovered, and these are then, to produce a con-ductive connection between the conductors and boreholes, pro-vided with a layer of copper by the action of a chemical copper bath.
3. A process according to claim 1, in which the entire surface is first coated with a layer of copper by the action of a chemical copper bath, then the lacquer layer is applied, leaving the boreholes and soldering eyes uncovered.
4. A process according to claim 1, 2 or 3, in which the copper lamination is etched away by means of an acidic etching solution or an alkaline etching solution.
5. A process according to claim 1, 2 or 3, in which the copper lamination is etched away by means of an acidic ammonium persulphate solution or an ammoniacal solution of sodium chlorite.
6. A process according to claim 1, 2 or 3, in which the substrate material is printed by a positive process.
7. A process according to claim 1, 2 or 3, in which the substrate material is printed by a positive printing process using an alkali soluble silk-screen printing ink.
8. A process according to claim 1, 2 or 3, in which the product obtained is provided with a covering of a lead/tin alloy.
9. A process according to claim 1, in which the etch resist is removed by means of a 3 to 5% sodium hydrox-ide solution or an organic solvent.
10. A process according to claim 9, in which the etch resist is removed by means of methylene chloride.
11. A process according to claim 1, 2 or 3, in which the lacquer is a solder-blocking lacquer.
12. A process according to claim 1, 2 or 3, in which a stabilised chemical copper bath is used.
13. A process according to claim 1, 2 or 3, in which a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, and an alkali cyanide as stabiliser.
14. A process according to claim 1, 2 or 3, in which a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, and an alkali cyanide as stabiliser and a selenium compound.
15. A process according to claim 1, 2 or 3, in which the product obtained is provided with a covering of a lead/tin alloy, the lead/tin alloy being applied in the form of a melt by the action of very hot air or by reductive deposition from a chemical tin bath.
16. A process according to claim 1, 2 or 3, in which a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, and an alkali cyanide as stabiliser and an alkali metal seleno-cyanate.
17. A process according to claim 1, 2 or 3, in which a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, and an alkali cyanide as stabiliser and a selenium compound, the selenium compound being present in an amount of from 0.1 to 0.3 mg/litre of a bath liquid.
18. A process according to claim 1, 2 or 3, in which a chemical copper bath is used, containing as the essential constituents a copper salt, a complex former, formaldehyde, and an alkali cyanide as stabiliser, the alkali cyanide being sodium cyanide present in an amount of from 15 to 30 mg/litre.
CA000357874A 1979-08-09 1980-08-08 Process for the manufacture of printed circuits Expired CA1152226A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP2932536.8 1979-08-09
DE19792932536 DE2932536A1 (en) 1979-08-09 1979-08-09 METHOD FOR PRODUCING PRINTED CIRCUITS

Publications (1)

Publication Number Publication Date
CA1152226A true CA1152226A (en) 1983-08-16

Family

ID=6078196

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000357874A Expired CA1152226A (en) 1979-08-09 1980-08-08 Process for the manufacture of printed circuits

Country Status (10)

Country Link
JP (1) JPS5629395A (en)
CA (1) CA1152226A (en)
CH (1) CH647372A5 (en)
DE (1) DE2932536A1 (en)
FR (1) FR2463569B1 (en)
GB (1) GB2057774B (en)
IE (1) IE49971B1 (en)
IT (1) IT1131716B (en)
NL (1) NL8003939A (en)
SE (1) SE454476B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0090900B1 (en) * 1982-04-05 1987-02-11 Kanto Kasei Co., Ltd. Process of manufacturing printed wiring boards and printed wiring boards manufactured by the same
FI88241C (en) * 1990-10-30 1993-04-13 Nokia Mobile Phones Ltd FOERFARANDE FOER FRAMSTAELLNING AV KRETSKORT
US5358602A (en) * 1993-12-06 1994-10-25 Enthone-Omi Inc. Method for manufacture of printed circuit boards
US5620612A (en) * 1995-08-22 1997-04-15 Macdermid, Incorporated Method for the manufacture of printed circuit boards

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1378154A (en) * 1962-09-24 1964-11-13 North American Aviation Inc Electrical interconnections for printed circuit boards
US3269861A (en) * 1963-06-21 1966-08-30 Day Company Method for electroless copper plating
DE1690224B1 (en) * 1967-08-29 1971-03-25 Standard Elek K Lorenz Ag BATHROOM FOR ELECTRONIC COPPER PLATING OF PLASTIC PANELS
FR2128355A1 (en) * 1971-03-01 1972-10-20 Fernseh Gmbh
JPS5489276A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Method of producing printed board

Also Published As

Publication number Publication date
IE49971B1 (en) 1986-01-22
SE454476B (en) 1988-05-02
DE2932536A1 (en) 1981-02-26
JPS5629395A (en) 1981-03-24
FR2463569A1 (en) 1981-02-20
IT1131716B (en) 1986-06-25
IE801669L (en) 1981-02-09
SE8005443L (en) 1981-02-10
NL8003939A (en) 1981-02-11
IT8023530A0 (en) 1980-07-18
GB2057774B (en) 1983-09-07
FR2463569B1 (en) 1985-09-20
CH647372A5 (en) 1985-01-15
GB2057774A (en) 1981-04-01

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