JPS62598B2 - - Google Patents
Info
- Publication number
- JPS62598B2 JPS62598B2 JP53150280A JP15028078A JPS62598B2 JP S62598 B2 JPS62598 B2 JP S62598B2 JP 53150280 A JP53150280 A JP 53150280A JP 15028078 A JP15028078 A JP 15028078A JP S62598 B2 JPS62598 B2 JP S62598B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- electrolytic copper
- hole
- chemical
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 67
- 239000000126 substance Substances 0.000 claims description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 26
- 238000002161 passivation Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 31
- 238000000034 method Methods 0.000 description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 7
- 239000000654 additive Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- NLHHRLWOUZZQLW-UHFFFAOYSA-N Acrylonitrile Chemical compound C=CC#N NLHHRLWOUZZQLW-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 2
- 239000011134 resol-type phenolic resin Substances 0.000 description 2
- POAOYUHQDCAZBD-UHFFFAOYSA-N 2-butoxyethanol Chemical compound CCCCOCCO POAOYUHQDCAZBD-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- JZULKTSSLJNBQJ-UHFFFAOYSA-N chromium;sulfuric acid Chemical compound [Cr].OS(O)(=O)=O JZULKTSSLJNBQJ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- -1 imidazole compound Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000012046 mixed solvent Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 150000003755 zirconium compounds Chemical class 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は印刷配線板の製造方法の改良に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing printed wiring boards.
従来、印刷配線板を製造するには、銅張積層板
を素材とし、銅箔を選択エツチングして所望の回
路パターンを形成する、いわゆるサブトラクテイ
ブ法が採用されている。しかしながら、このサブ
トラクテイブ法はエツチング液の排出等による公
害問題や、サイドエツチングによるパターン精度
の低下、その他経済性の悪さ等の問題がある。 Conventionally, in order to manufacture printed wiring boards, a so-called subtractive method has been adopted in which a copper-clad laminate is used as a material and copper foil is selectively etched to form a desired circuit pattern. However, this subtractive method has problems such as pollution caused by discharge of etching solution, reduced pattern accuracy due to side etching, and poor economic efficiency.
このようなことから、最近、公害誘発の抑制、
パターン精度の向上等を改善するために、化学メ
ツキだけでパターンを形成するアデイテイブ法
や、化学メツキと電気メツキを併用したセミアデ
イテイブ法が注目されている。 For this reason, recent efforts have been made to reduce pollution
In order to improve pattern accuracy, additive methods in which patterns are formed using only chemical plating, and semi-additive methods in which chemical plating and electroplating are used together are attracting attention.
しかしながら、前者のアデイテイブ法は前記サ
ブトラクテイブ法に比べてスルホールの信頼性が
劣るため、実用的ではない。他方、後者のセミア
デイテイブ法はアデイテイブ法に比べてパターン
の信頼性が向上するものの、下地となる化学メツ
キ層を塩化第二鉄水溶液等で溶解除去する場合、
スルホール内壁及び回路パターンの電気銅メツキ
膜もエツチングされ、しかもスルホール内壁は回
路パターンの部分に比してエツチングの液切れが
悪いために、エツチング度合が該回路パターンの
2〜5倍となる。その結果、スルホール内壁と回
路パターンとの電気メツキ膜間の厚さにバラツキ
が生じて接続性が低下し、しかもスルホール内壁
の断線が起り易く信頼性に欠ける印刷配線板とな
る問題があつた。 However, the former additive method is not practical because the reliability of through holes is inferior to that of the subtractive method. On the other hand, although the latter semi-additive method improves the reliability of the pattern compared to the additive method, when the underlying chemical plating layer is dissolved and removed with a ferric chloride aqueous solution,
The inner walls of the through holes and the electrolytic copper plating film of the circuit pattern are also etched, and since the inner walls of the through holes drain less easily than the circuit pattern, the degree of etching is 2 to 5 times that of the circuit pattern. As a result, there is a problem in that the thickness between the electroplated film on the inner wall of the through hole and the circuit pattern varies, resulting in poor connectivity, and furthermore, the inner wall of the through hole is easily disconnected, resulting in an unreliable printed wiring board.
一方、上記セミアデイテイブ法の改良手段とし
て、下地となる化学メツキ層を溶解除去する前
に、スルホール及び回路パターンの電気銅メツキ
膜上に錫メツキ、半田メツキを施して、化学メツ
キ層のエツチング時におけるスルホール及び回路
パターンの電気銅メツキ膜のエツチングを防止す
ることが行なわれている。しかし、この方法にあ
つては印刷配線板の製造工程が煩雑化するばかり
か、新たに錫半田メツキの設備が必要となり、生
産性の低下及び生産コストの高騰化を招く欠点が
ある。 On the other hand, as a means of improving the above-mentioned semi-additive method, before dissolving and removing the underlying chemical plating layer, tin plating and solder plating are applied to the electrolytic copper plating film of the through holes and circuit patterns, so that the chemical plating layer can be etched. Etching of the electrolytic copper plating film of through holes and circuit patterns has been prevented. However, this method not only complicates the manufacturing process of the printed wiring board, but also requires new tin solder plating equipment, which has the disadvantage of lowering productivity and increasing production costs.
これに対し、本発明者は上記欠点を解消するた
めに鋭意研究を重ねた結果、電気銅メツキ処理に
より形成されたスルホール内壁及び回路パターン
上に半田付が可能な不活性化層を形成することに
よつて、スルホール内壁及び回路パターン以外の
下地としての化学メツキ層部分をエツチング液で
溶解除去するに際し、スルホール内壁及び回路パ
ターンの電気銅メツキ膜のエツチングを前記不活
性化層の保護作用により防止でき、さらに製造後
の電気銅メツキ層を不活性化層で外界から保護で
きると共に、該スルホール内壁及び回路パターン
への半田付時にその上の不活性化層が一部残存し
ても良好な半田付けを遂行でき、もつて長期間安
定した半田付性を有し、かつ接続性が良好でスル
ホール内壁の断線のない極めて信頼性の高い印刷
配線板の製造法を見い出した。 On the other hand, as a result of extensive research in order to eliminate the above-mentioned drawbacks, the inventors of the present invention formed a solderable passivation layer on the inner wall of the through-hole and the circuit pattern formed by electrolytic copper plating. Accordingly, when removing the chemically plated layer as a base other than the inner wall of the through hole and the circuit pattern by dissolving and removing it with an etching solution, the protective action of the passivation layer prevents etching of the electrolytic copper plating film of the inner wall of the through hole and the circuit pattern. Furthermore, the electrolytic copper plating layer after manufacture can be protected from the outside world with a passivation layer, and even if a portion of the passivation layer above it remains when soldering to the inner wall of the through hole and the circuit pattern, good soldering can be achieved. We have discovered a method for producing an extremely reliable printed wiring board that can be easily attached, has stable solderability over a long period of time, has good connectivity, and has no disconnection on the inner wall of the through hole.
すなわち、本発明方法はスルホール孔を有する
化学メツキ用接着剤付基板に化学メツキ処理を施
して化学メツキ層を形成する工程と、孔内壁及び
所望の回路パターン領域を除く化学メツキ層部分
にメツキレジスト膜を被膜する工程と、電気銅メ
ツキ処理を施してメツキレジスト膜から露出した
孔内壁及び回路パターン領域に所望厚さの電気銅
メツキ膜を形成する工程と、電気銅メツキ膜表面
に半田付けが可能な材料からなる不活性化層を被
膜する工程と、メツキレジスト膜を除去後、露出
する化学メツキ層部分を溶解除去せしめる工程
と、を具備したことを特徴とするものである。 That is, the method of the present invention includes the steps of performing chemical plating treatment on a substrate with chemical plating adhesive having through-hole holes to form a chemical plating layer, and applying a plating resist to the chemical plating layer portion excluding the inner wall of the hole and the desired circuit pattern area. A process of coating a film, a process of performing an electrolytic copper plating process to form an electrolytic copper plating film of a desired thickness on the inner wall of the hole and the circuit pattern area exposed from the plating resist film, and a process of applying solder to the surface of the electrolytic copper plating film. This method is characterized by comprising a step of coating a passivation layer made of a material that can be used, and a step of dissolving and removing the exposed chemical plating layer portion after removing the plating resist film.
本発明に使用する化学メツキ用接着剤として
は、例えばアクリロニトリルゴムとノボラツク
型、レゾール型のフエノール樹脂、或いはエポキ
シ樹脂とからなり、必要に応じてジルコニウム化
合物、シリカ粉を配合したもの等を挙げることが
できる。 Examples of the chemical plating adhesive used in the present invention include those made of acrylonitrile rubber and novolak type or resol type phenolic resin or epoxy resin, and blended with a zirconium compound or silica powder as necessary. I can do it.
本発明に使用する基板としては、エポキシ樹脂
などから成る絶縁基板、或いは内層板を有する多
層基板等を挙げることができる。 Examples of the substrate used in the present invention include an insulating substrate made of epoxy resin or the like, a multilayer substrate having an inner layer plate, and the like.
本発明における化学メツキ層とは、化学銅メツ
キ層或いは化学ニツケルメツキ層であるが、とく
に化学銅メツキ層は電気抵抗が低く、メツキ厚さ
を均一にできるため有益である。 The chemical plating layer in the present invention is a chemical copper plating layer or a chemical nickel plating layer, and the chemical copper plating layer is particularly useful because it has a low electrical resistance and can make the plating thickness uniform.
本発明に使用する不活性化層の材料は半田付時
に半田乗りを阻害せず、かつ下地としての化学メ
ツキ層のエツチング液に対して耐溶解性が優れた
ものであり、具体的にはイミダゾール化合物又は
その塩類等を挙げることができる。 The material for the passivating layer used in the present invention does not inhibit solder adhesion during soldering and has excellent dissolution resistance to the etching solution for the chemical plating layer as a base. Examples include compounds or salts thereof.
なお、本発明においては、化学メツキ層を電気
銅メツキ膜の材料と異なる化学ニツケルメツキ層
で形成し、かつ不活性化層の材料を選定すること
によつて、電気銅メツキ膜のみに不活性化層を被
着できることから、電気銅メツキ処理後にメツキ
レジスト膜を除去した後、化学ニツケルメツキ層
が露出した状態で不活性化層を形成してもよい。 In addition, in the present invention, by forming the chemical plating layer with a chemical nickel plating layer different from the material of the electrolytic copper plating film and selecting the material of the passivation layer, it is possible to inactivate only the electrolytic copper plating film. After the plating resist film is removed after the electrolytic copper plating process, the passivation layer may be formed with the chemical nickel plating layer exposed.
次に、本発明の実施例を第1図〜第8図を参照
して説明する。 Next, embodiments of the present invention will be described with reference to FIGS. 1 to 8.
実施例
まず、第1図に示す如くエポキシ樹脂製の基板
1に、アクリロニトリルゴム40重量部、レゾール
型フエノール樹脂20重量部、ビスフエノール型エ
ポキシ樹脂20重量部、シリカゲル10重量部及び硬
化剤10重量部をメチルエチルケトン−ブチルセル
ソルブ混合溶媒で溶媒した化学メツキ用接着剤を
デイツプ方式で塗布し、風乾後160℃で40分間乾
燥して厚さ20μmの接着剤層2を形成した。つづ
いて、この基板の所望部分を第2図に示す如くド
リルで穴明け加工してスルホール孔3を設けた
後、クロム−硫酸混液で親水化処理し、常法に従
つて活性化処理し、さらに化学銅メツキ液に浸漬
してスルホール孔3を含む基板1全面に化学ニツ
ケルメツキ層4を形成した(第3図図示)。その
後、第4図に示す如くスルホール孔3内壁及び所
定の回路パターン領域を除く化学ニツケルメツキ
層4部分にマスク印刷でメツキレジスト膜5を被
覆し乾燥した後、硫酸溶液15%で活性化し、電気
銅メツキ処理を施してスルホール孔3及び回路パ
ターン領域の化学ニツケルメツキ層上に電気銅メ
ツキ膜6を形成した(第5図図示)。Example First, as shown in FIG. 1, 40 parts by weight of acrylonitrile rubber, 20 parts by weight of resol-type phenolic resin, 20 parts by weight of bisphenol-type epoxy resin, 10 parts by weight of silica gel, and 10 parts by weight of curing agent were placed on an epoxy resin substrate 1 as shown in FIG. A chemical plating adhesive containing a mixed solvent of methyl ethyl ketone and butyl cellosolve was applied using a dip method, air-dried, and then dried at 160° C. for 40 minutes to form an adhesive layer 2 with a thickness of 20 μm. Next, as shown in FIG. 2, a desired portion of this substrate is drilled to form a through hole 3, and then treated with a chromium-sulfuric acid mixture to make it hydrophilic, and activated according to a conventional method. Furthermore, a chemical nickel plating layer 4 was formed on the entire surface of the substrate 1 including the through holes 3 by immersing it in a chemical copper plating solution (as shown in FIG. 3). Thereafter, as shown in FIG. 4, a plating resist film 5 is coated by mask printing on the chemical nickel plating layer 4 excluding the inner wall of the through hole 3 and a predetermined circuit pattern area, and after drying, it is activated with a 15% sulfuric acid solution, and electrolytic copper is applied. A plating process was performed to form an electrolytic copper plating film 6 on the chemical nickel plating layer in the through holes 3 and the circuit pattern area (as shown in FIG. 5).
次いで、電気銅メツキ処理後の基板をイミダゾ
ール化合物溶液(四国化成工業(株)製商品名;
グリコートL)に5分間浸漬した後水洗し、スル
ホール孔3及び回路パターン領域の電気銅メツキ
膜6上に半田付可能な不活性化層7を被覆した
(第6図図示)。その後、第7図の如くメツキレジ
スト膜5を剥離した後、過硫酸アンモニウム250
g/、ベンゾトリアゾール1g/からなるエ
ツチング液に浸漬して露出した化学ニツケルメツ
キ層4部分をエツチングして第8図の如きスルホ
ール8及び回路パターン9を有する印刷配線板1
0を得た。 Next, the substrate after the electrolytic copper plating treatment was treated with an imidazole compound solution (trade name, manufactured by Shikoku Kasei Kogyo Co., Ltd.;
After immersion in Glycoat L) for 5 minutes and washing with water, a solderable passivation layer 7 was coated on the electrolytic copper plating film 6 in the through-hole holes 3 and the circuit pattern area (as shown in FIG. 6). After that, as shown in FIG. 7, after peeling off the plating resist film 5, ammonium persulfate 250
A printed wiring board 1 having through holes 8 and a circuit pattern 9 as shown in FIG.
I got 0.
得られた印刷配線板はエツチング工程での電気
銅メツキ膜の溶解が全くなく、接続性が良好で断
線のない信頼性の高いスルホールが形成されてい
ることがわかつた。また、この印刷配線板を1カ
月間放置後、そのスルホールに部品のリード線を
半田により実装したところ、はんだ揚り率は95%
以上で、部品接続信頼性も良好であつた。 It was found that in the obtained printed wiring board, the electrolytic copper plating film did not dissolve at all during the etching process, and highly reliable through holes with good connectivity and no disconnection were formed. In addition, after leaving this printed wiring board for one month, we soldered component lead wires to the through holes, and the soldering rate was 95%.
As described above, component connection reliability was also good.
以上詳述した如く、本発明によればスルホール
内壁及び回路パターンの電気銅メツキ膜のエツチ
ングを防止でき、さらに、製造後の電気銅メツキ
膜を半田付性の阻害化を招くことなく、外界から
保護でき、もつて接続性が良好でスルホール内壁
の断線がなく、しかも長期間放置しても良好な半
田付性を有する極めて信頼性の高い印刷配線板を
提供できるものである。 As detailed above, according to the present invention, it is possible to prevent etching of the electrolytic copper plating film on the inner wall of the through hole and the circuit pattern, and furthermore, it is possible to prevent the electrolytic copper plating film after manufacture from being exposed to the outside world without impeding solderability. It is possible to provide an extremely reliable printed wiring board that can be protected, has good connectivity, has no disconnection on the inner wall of the through hole, and has good solderability even after being left unused for a long period of time.
第1図〜第8図は本発明の実施例における印刷
配線板の製造工程を示す断面図である。
1……基板、2……接着剤層、3……スルホー
ル孔、4……化学ニツケルメツキ層、5……メツ
キレジスト膜、6……電気銅メツキ膜、7……不
活性化層、8……スルホール、9……回路パター
ン、10……印刷配線板。
1 to 8 are cross-sectional views showing the manufacturing process of a printed wiring board in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Adhesive layer, 3... Through-hole hole, 4... Chemical nickel plating layer, 5... Plating resist film, 6... Electrolytic copper plating film, 7... Passivation layer, 8... ...Through hole, 9...Circuit pattern, 10...Printed wiring board.
Claims (1)
基板に化学メツキ処理を施して化学メツキ層を形
成する工程と、孔内壁及び所望の回路パターン領
域を除く化学メツキ層部分にメツキレジスト膜を
被覆する工程と、電気銅メツキ処理を施してメツ
キレジスト膜から露出した孔内壁及び回路パター
ン領域に所望厚さの電気銅メツキ膜を形成する工
程と、電気銅メツキ膜表面に半田付けが可能な材
料からなる不活性化層を被覆する工程と、メツキ
レジスト膜を除去後、露出する化学メツキ層部分
を溶解除去せしめる工程と、を具備したことを特
徴とする印刷配線板の製造方法。1. A step of forming a chemical plating layer by performing chemical plating treatment on a chemical plating adhesive-attached substrate having through-hole holes, and a step of coating the chemical plating layer portion with a plating resist film excluding the inner wall of the hole and the desired circuit pattern area. , a step of performing electrolytic copper plating to form an electrolytic copper plating film of a desired thickness on the inner wall of the hole and the circuit pattern area exposed from the plating resist film, and a material that can be soldered to the surface of the electrolytic copper plating film. 1. A method for producing a printed wiring board, comprising the steps of: coating a passivation layer; and removing the plating resist film, then dissolving and removing the exposed chemical plating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15028078A JPS5577196A (en) | 1978-12-05 | 1978-12-05 | Method of fabricating printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15028078A JPS5577196A (en) | 1978-12-05 | 1978-12-05 | Method of fabricating printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5577196A JPS5577196A (en) | 1980-06-10 |
JPS62598B2 true JPS62598B2 (en) | 1987-01-08 |
Family
ID=15493510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15028078A Granted JPS5577196A (en) | 1978-12-05 | 1978-12-05 | Method of fabricating printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5577196A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4983867A (en) * | 1972-12-20 | 1974-08-12 | ||
JPS5027033A (en) * | 1973-07-11 | 1975-03-20 |
-
1978
- 1978-12-05 JP JP15028078A patent/JPS5577196A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4983867A (en) * | 1972-12-20 | 1974-08-12 | ||
JPS5027033A (en) * | 1973-07-11 | 1975-03-20 |
Also Published As
Publication number | Publication date |
---|---|
JPS5577196A (en) | 1980-06-10 |
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