CA1125421A - Solid state image sensor - Google Patents
Solid state image sensorInfo
- Publication number
- CA1125421A CA1125421A CA312,252A CA312252A CA1125421A CA 1125421 A CA1125421 A CA 1125421A CA 312252 A CA312252 A CA 312252A CA 1125421 A CA1125421 A CA 1125421A
- Authority
- CA
- Canada
- Prior art keywords
- sensor
- substrate
- solid state
- state image
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000005036 potential barrier Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
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- 238000003860 storage Methods 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101150077457 ACOX1 gene Proteins 0.000 description 1
- 241001497337 Euscorpius gamma Species 0.000 description 1
- 244000088959 Ochrosia oppositifolia Species 0.000 description 1
- 241001080526 Vertica Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- MYWUZJCMWCOHBA-VIFPVBQESA-N methamphetamine Chemical compound CN[C@@H](C)CC1=CC=CC=C1 MYWUZJCMWCOHBA-VIFPVBQESA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- ACWBQPMHZXGDFX-QFIPXVFZSA-N valsartan Chemical class C1=CC(CN(C(=O)CCCC)[C@@H](C(C)C)C(O)=O)=CC=C1C1=CC=CC=C1C1=NN=NN1 ACWBQPMHZXGDFX-QFIPXVFZSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
- H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
- H01J29/10—Screens on or from which an image or pattern is formed, picked up, converted or stored
- H01J29/36—Photoelectric screens; Charge-storage screens
- H01J29/39—Charge-storage screens
- H01J29/45—Charge-storage screens exhibiting internal electric effects caused by electromagnetic radiation, e.g. photoconductive screen, photodielectric screen, photovoltaic screen
- H01J29/451—Charge-storage screens exhibiting internal electric effects caused by electromagnetic radiation, e.g. photoconductive screen, photodielectric screen, photovoltaic screen with photosensitive junctions
- H01J29/453—Charge-storage screens exhibiting internal electric effects caused by electromagnetic radiation, e.g. photoconductive screen, photodielectric screen, photovoltaic screen with photosensitive junctions provided with diode arrays
- H01J29/455—Charge-storage screens exhibiting internal electric effects caused by electromagnetic radiation, e.g. photoconductive screen, photodielectric screen, photovoltaic screen with photosensitive junctions provided with diode arrays formed on a silicon substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/571—Control of the dynamic range involving a non-linear response
- H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/73—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using interline transfer [IT]
Abstract
ABSTRACT OF THE DISCLOSURE
A solid state image sensor of the so-called, inter-line transfer system with an overflow drain region is disclosed.
The solid state image sensor comprises a semiconductor substrate, a plurality of sensor regions formed as a position of the substrate which is arranged in row and column direction. A shift register is provided at one side of the row of the sensor regions and an overflow drain region is provided at another side of the row of the sensor regions. A transfer electrode provided over a portion of the shift register and a transfer gate region which is between the picture element and the shift register to which is applied a clock voltage to both transfer signal changes in the shift register and to form a potential barrier at the transfer gate region during horizontal blanking intervals. A common sensor electrode is provided over the sensor region and a overflow control region which is located between the sensor region and the overflow drain region.
Predetermined voltages are applied to the sensor electrode,at predetermined timings,in the selected horizontal blanking intervals. The voltages applied to the sensor electrode at the selected horizontal blanking interval gradually increase so as to achieve a so-called gamma correction.
A solid state image sensor of the so-called, inter-line transfer system with an overflow drain region is disclosed.
The solid state image sensor comprises a semiconductor substrate, a plurality of sensor regions formed as a position of the substrate which is arranged in row and column direction. A shift register is provided at one side of the row of the sensor regions and an overflow drain region is provided at another side of the row of the sensor regions. A transfer electrode provided over a portion of the shift register and a transfer gate region which is between the picture element and the shift register to which is applied a clock voltage to both transfer signal changes in the shift register and to form a potential barrier at the transfer gate region during horizontal blanking intervals. A common sensor electrode is provided over the sensor region and a overflow control region which is located between the sensor region and the overflow drain region.
Predetermined voltages are applied to the sensor electrode,at predetermined timings,in the selected horizontal blanking intervals. The voltages applied to the sensor electrode at the selected horizontal blanking interval gradually increase so as to achieve a so-called gamma correction.
Description
i:~Z~Zl BACKGRO~IND OF THE INVENTION
Field of the Invention The ~resent invention relates generally to a solid state image sensor which forms a charge coupled device (which will be hereina~ter referred to simply as a CCD), and is directed more parti-cularly to a solid state image sensor Or an interline transfer system.
BJ~JEF DESCRIPTIOI~ OF T~lE DRAWIMGS
Fig, 1 is a schematic diagram showing the construction Or a solid state image sensor device of an interline transfer system;
Fig, 2 is a plan view showing a main part Or an example of the solid state image sensor according to the present invention;
Figs. 3 and 4 are cross-sectlonal views taken on lines Jll-lll and IV-IV in Pig.2;
Fig. 5 is a graph showing the relation between a voltage applied to a sensor area anc? an overr~ow control region and a minimum potential;
Figs, 6A, 6~ and 6C are voltage timing dia@rams used ~or explaining the operation Dt the invention;
Figs. 7 to 9. inclusive, are potential diagrams showing respective modes of the image sensor Or the invention;
FiB. 10 is a diagram showing a stored charge in the sensor area at respective times when the intensity Or light irradiated to the ima~e sensor is varied;
Fig. 11 is a graph showing a gamma correction curve; and Fig. 12 is a diagram showing a minimum potential at an automatic sensil~ilit~ adjusting mode.
B
:llZ54Zl Description of the Prior Art .
An ordinary CCD solid state image sensor of the interline transfer system is formed, such as shown in Fig. 1, on a common semiconductor substrate, for example. silicon substrate where there are provided a plurality of light receivin~ portions i.e. sensor areas l. ~ese areas will define picture elements, disposed in one direction (which will be hereinafter referred to as a horizon~al direction) and fur-there disp~sed in a direction perpendicular to the horizont 1 direction~hich latter direction will be hereinafter re~erred to as a vertical direction) to form rows and columns. A vertical shift register 2 of CCD co~struction is lo-cated along orle side of each of the sensor areas l which are arranged in the vertical direction. and a horizontal shift register 3 of CCD co~struction is located cann~ly at one end of each of the vertical shift registers 2.
For example, in a case Or ~elevision video image signal generation, during the vertical blanking interval signa], charges pr~ced in the sensor areas 1, in respc~nse to the a~nt of received light, are trans-ferred to the corresponding vertical shift registers 2. D~ring each of the horizontal blanking intervals eaeh Or the signal cnarges in each 2n of the vertical shift registers 2 is sequentially transferred to the horizontal shift register 3, and the signal charge is read out from an output terminal t connected to the horizontal shift register 3 in each of the horizontal video intervals. me char~e transfer, fran each of the ser areas 1 to the vertical shift register
Field of the Invention The ~resent invention relates generally to a solid state image sensor which forms a charge coupled device (which will be hereina~ter referred to simply as a CCD), and is directed more parti-cularly to a solid state image sensor Or an interline transfer system.
BJ~JEF DESCRIPTIOI~ OF T~lE DRAWIMGS
Fig, 1 is a schematic diagram showing the construction Or a solid state image sensor device of an interline transfer system;
Fig, 2 is a plan view showing a main part Or an example of the solid state image sensor according to the present invention;
Figs. 3 and 4 are cross-sectlonal views taken on lines Jll-lll and IV-IV in Pig.2;
Fig. 5 is a graph showing the relation between a voltage applied to a sensor area anc? an overr~ow control region and a minimum potential;
Figs, 6A, 6~ and 6C are voltage timing dia@rams used ~or explaining the operation Dt the invention;
Figs. 7 to 9. inclusive, are potential diagrams showing respective modes of the image sensor Or the invention;
FiB. 10 is a diagram showing a stored charge in the sensor area at respective times when the intensity Or light irradiated to the ima~e sensor is varied;
Fig. 11 is a graph showing a gamma correction curve; and Fig. 12 is a diagram showing a minimum potential at an automatic sensil~ilit~ adjusting mode.
B
:llZ54Zl Description of the Prior Art .
An ordinary CCD solid state image sensor of the interline transfer system is formed, such as shown in Fig. 1, on a common semiconductor substrate, for example. silicon substrate where there are provided a plurality of light receivin~ portions i.e. sensor areas l. ~ese areas will define picture elements, disposed in one direction (which will be hereinafter referred to as a horizon~al direction) and fur-there disp~sed in a direction perpendicular to the horizont 1 direction~hich latter direction will be hereinafter re~erred to as a vertical direction) to form rows and columns. A vertical shift register 2 of CCD co~struction is lo-cated along orle side of each of the sensor areas l which are arranged in the vertical direction. and a horizontal shift register 3 of CCD co~struction is located cann~ly at one end of each of the vertical shift registers 2.
For example, in a case Or ~elevision video image signal generation, during the vertical blanking interval signa], charges pr~ced in the sensor areas 1, in respc~nse to the a~nt of received light, are trans-ferred to the corresponding vertical shift registers 2. D~ring each of the horizontal blanking intervals eaeh Or the signal cnarges in each 2n of the vertical shift registers 2 is sequentially transferred to the horizontal shift register 3, and the signal charge is read out from an output terminal t connected to the horizontal shift register 3 in each of the horizontal video intervals. me char~e transfer, fran each of the ser areas 1 to the vertical shift register
2 is carried out. for example, at every other horizontal line, and at odd field inten~als the signal in each of the sensor areas 1 at every other horizontal line is read out. During even field int~vals the signal in each of the sensor areas l re~i~g at every o~her h~
zontal line is read out to define the so-called interlacing.
In the a~ove solid state inage sensor device, it is desired that a so-called gamma (~) correction is effected so as to keep a predetermined relation between an light input to the image -}
il~S~
sensor and a~ electrical output signal thererrDm. It may be con-sidered in the gamma correction method that, for example. the over-rlow of electric charges to an overflow drain region, which is provided adjacent the sensor areas to prevent a blooming, is controlled.
ln this case, if an electrode is used for that purpose the potential barrier between the sensor area and overflow drain regior.
oantrols the overflow amDunt and hence effects the gamma correction and is provided independently from other electrDdes. Such a defect requires that a oonductive layer for formmg the above electr~de i9 a~d;tionally required with the result that the construction ~nd n~nufac~ure beccmes more complicated.
O~JECTS A~nD SU~AR~' OF THE ~ 1ENTJO~' Accordingly, it is an object of the present invention to prDvide a no~e] solid state image sensor free from the defects ir~erent in prior art solid state image sens~rs.
It is another object o~ the invention to provide a solid state image sens~r in which th~ erflow Or an electric charge to an ~verflDw drain region is positively controlled to carry out gamma correction.
- ~ccording to one aspect of th~ ~resent invention, t~ere i~ provided:
A ~olid state image ~ensor compri~ing:
a) a semiconductor ~ubstrate, b) a plurality of sensor re~ions formed of portions of said substrate arranged in row and column directions, which are able to store signal charges of predetermined amount during a predetermined period, c~ a shift register formed of a portion of said substrate associated with each row of said sensor regions, d) an overflow drain formed of a portion of said substrate associated with each row of said senor regions at the opposite ~ide of ~aid row of sAid sensor regions with respect to said shift register, e) first means to form a first potential barrier for signal charges between said sensor regions and said shift register during predetermined intervals sequentially ~ncreases in said predetermined period, f) second means to form a second potential barrier for signal charges between said sensor regions and said overflow drain region, said second potential barrier being lower than said first potential barrie~
during said predetermined intervals, and to form potential wells at ~aid sensor regions to store signal charges, the amount of signal charges to be stored in said potential well being defined by said second potenti~l barrier and said potential well, and, g) third means to form said second potential barrier and potential well such that the said predeter-mined amount of signal charges to be stored,in said sensor regions, are enabled at timings at inter-mittently selected intervals from ~aid predeter-mined intervals.
lhe other objects, features and advantages of the ~resent lnvention will be ap~nt from the follo~ng description taken in conjunction with the acox~nying drawnngs.
~l~S4~:1 DECCr~lPTlO~i OF THE PREFET~`RED E~P.ODIM~ T_ The present invention uill be hereinafter described In an example Or the solit~ state in!a~e sensor according to the present invention, similar to that sho~n in Fig. 1., there are located on a commDn semioonductor substrate, a number of sensor æeas 1 i.e. light receiving æeas Ln hDrizontal and vertical directions, and vertical 2 and horizontal shift register 3, respectively.
U'ith reîerence to Figs 1 to 4. an example ot the solid state image sensor according to the present invention ~ill be described.
Fig. 2 sho~s a part ~ an i~rage sensor in ~hich the sensor areas 1 and essential parts in association therewith are shown, and Figs.
zontal line is read out to define the so-called interlacing.
In the a~ove solid state inage sensor device, it is desired that a so-called gamma (~) correction is effected so as to keep a predetermined relation between an light input to the image -}
il~S~
sensor and a~ electrical output signal thererrDm. It may be con-sidered in the gamma correction method that, for example. the over-rlow of electric charges to an overflow drain region, which is provided adjacent the sensor areas to prevent a blooming, is controlled.
ln this case, if an electrode is used for that purpose the potential barrier between the sensor area and overflow drain regior.
oantrols the overflow amDunt and hence effects the gamma correction and is provided independently from other electrDdes. Such a defect requires that a oonductive layer for formmg the above electr~de i9 a~d;tionally required with the result that the construction ~nd n~nufac~ure beccmes more complicated.
O~JECTS A~nD SU~AR~' OF THE ~ 1ENTJO~' Accordingly, it is an object of the present invention to prDvide a no~e] solid state image sensor free from the defects ir~erent in prior art solid state image sens~rs.
It is another object o~ the invention to provide a solid state image sens~r in which th~ erflow Or an electric charge to an ~verflDw drain region is positively controlled to carry out gamma correction.
- ~ccording to one aspect of th~ ~resent invention, t~ere i~ provided:
A ~olid state image ~ensor compri~ing:
a) a semiconductor ~ubstrate, b) a plurality of sensor re~ions formed of portions of said substrate arranged in row and column directions, which are able to store signal charges of predetermined amount during a predetermined period, c~ a shift register formed of a portion of said substrate associated with each row of said sensor regions, d) an overflow drain formed of a portion of said substrate associated with each row of said senor regions at the opposite ~ide of ~aid row of sAid sensor regions with respect to said shift register, e) first means to form a first potential barrier for signal charges between said sensor regions and said shift register during predetermined intervals sequentially ~ncreases in said predetermined period, f) second means to form a second potential barrier for signal charges between said sensor regions and said overflow drain region, said second potential barrier being lower than said first potential barrie~
during said predetermined intervals, and to form potential wells at ~aid sensor regions to store signal charges, the amount of signal charges to be stored in said potential well being defined by said second potenti~l barrier and said potential well, and, g) third means to form said second potential barrier and potential well such that the said predeter-mined amount of signal charges to be stored,in said sensor regions, are enabled at timings at inter-mittently selected intervals from ~aid predeter-mined intervals.
lhe other objects, features and advantages of the ~resent lnvention will be ap~nt from the follo~ng description taken in conjunction with the acox~nying drawnngs.
~l~S4~:1 DECCr~lPTlO~i OF THE PREFET~`RED E~P.ODIM~ T_ The present invention uill be hereinafter described In an example Or the solit~ state in!a~e sensor according to the present invention, similar to that sho~n in Fig. 1., there are located on a commDn semioonductor substrate, a number of sensor æeas 1 i.e. light receiving æeas Ln hDrizontal and vertical directions, and vertical 2 and horizontal shift register 3, respectively.
U'ith reîerence to Figs 1 to 4. an example ot the solid state image sensor according to the present invention ~ill be described.
Fig. 2 sho~s a part ~ an i~rage sensor in ~hich the sensor areas 1 and essential parts in association therewith are shown, and Figs.
3 and 4 are cross-sectional ~ie~s taken on lines III-TII and IV-IV
in Fi~. 2, respectively. In the rigures. 4 designates a semi-conductor substra-e,such as a silicon substrate, havinp P-type cond~ctivity,on the surrace Or hich there is coated an insulating -5a-~3 11254Zl layer 5Jsuch as a SiO2 layer. In the example illustrated in ~he figures, the vertical shift register 2 is formed as a buried channel .
To this end, a region 6, having an N-type conductivity which is ditrerent from the su~strate 4,is formed in the substrate 4 an~l the major sur-face ther~of is in a stripe or ~and shape along the pæ t which forlr the shift register 2. A cha~nel stopper region 7,having the same conductivity as the substrate 4 and having high i~purity concent-ration,is formed in the substrate 4 such that it separates the adjacent sensor areas 1 and shift register 2 as shown in Fig. 2 and faoes the major surface 4a. An overflow control region 8, h~ving the conductivity which is same as that of the substrate 4,is formed in the substrate 4, and an overflow drain region 9, having a N-type conductivit~ of high impurity concentration different from the substrate 4, is formed in the latter adjacent each of the sensor areas 1 through the overflow control region 8 and disposed to faoe the major surfaoe 4a. Also, a gate region 1(~ havin~ ne ~-type conductivitv,is formed in the substrate 4 between each of the sensor areas 1 and the shift registers 2 corresponding thereto.
Each of the shift registers 2 is formed of a transfer region 11 disposed in oorrespondence with each of the sensor areas 1 arranged on a vertical line. In the illustrated example, the vertical shift register 2 is formed as a 2-phase clock type. In this case, each of the transter re~ions 11 consists Or~ for example, a part including a relatively thin insulating layer 5A and a part including a thick insula-ting layer 5B. On the insulating layers 5A and 5B there are formed electrodes 12A and 12B to form a so-called transfer gate 13A and a sborage region 1 3B, respectively. Both the electrodes 1 2A and 1 2B in the transfer re~ion 11 are electrically connected.
Jn the example, as shown in Fig. 4, in order to provide a difrerence between the depths Or potentials in the transfer gate 1 3A
:llZ5~Zl and strage region 13B Or the vertical shift register Z~ the insulating layers 5 and 5B beneath the electr~des 12A and lZB are made o different t,hickness for each other. H~ever, it is also possible t-~at the potentials can be made of dif~er~ltdepth by utilizing the difrerence of ilrçNrity bulk concentrations instead of utilizing the diffe~ence between the thicknesses of the insulating layers. In this latter case, the insulating layers 5A an~ 5B beneath the transter and st~e ele-ctrodes 1 2A an~ 1 2B are equal. but a shallow region ha~ring P-type conductivity is formed beneath the transfer electrode 1 2A This P-type region car. be formed by, for example, carrying out ion implantation selectively.
The gate region 1 0,between each Or the sensor areas 1 and the corresponding vertical shift register 2, which has, for example, the same conductivity as the substrate 4. is formed with a region 14 in the substrate 4 and has an ~urity concentration higher than that of the substrate 4 and faces the major surface 4a thereof. E~xn the upper surface of the region 14 ext~ds the insu-lating layer 5, ror example, insulating layer 5B on which a gate ele-ctro~e 15 is coated. The gate electrode 15 of the gate region 10 corresponding to each of the sensor areas 1 and the electrodes 1 3A
and 1 3B o~ each of the transfer regions 11 in the vertical shift register 2, are a~y form~d as ~dwwn in Fig. 2 by a dotted line a, or ele-ctrically connected so as to be supplied with a ca~n v~ltage. In this case. even i~ the same voltage is applied to the respective electrodes of the gate region 10 and the transfer region 11, the impurity concent-rationC in the reE~ions 10 and 11 or the thicknesses of the insulating layers,are so selected that the minimum potentials in the respective regions are always shallow in the gate region. From every other transfer region l1, which are connected together and the connection le~ out are termir~s trl and tr2.
11~5~2~
rhe o~erflow control region 8 is- for example~ of the same conductivity as the substrate 4 and is formed or a region 16 which is formed in the substrate 4~ and is ~ her th~n the latter in ~l!purity concen-tration and faces the major surface 4a. A control electrode 17 is formed thro~-gh the insulating layer 5 on the region 16.
The sensor area 1 is formed by forming a sensor electrode 18 on the insulating layer 5 and through which light passes. me sensor electrode 18 and the control electrode 17 of the corresponding overflow control region 8 are formed of a cc~non continuous transparent ele-ctrode or connected electrically and to ~ich a c~n voltage is applied through a terminal tS~
The respective regions 6, 7, 9, 14 and 16 can be formed by a well known technique such as the selective diff~lsion method, ion implantation method or the like. The respective electrodes 15, 1 2A
and 12B are formed by sequentially depositing polycrystalline silicon layers, which are made low in resistance by an impurity doped thereinto, ~y a chemic 1 vapour deposition meth~d. me insulating layers are formed by o~idi~.ing the surfaces ot the layers and hence the transparent electroce, ~hich form the sensor electrode 18 and overflaw control electrode 17, is formed all over the insulating lay-er 5 A light shield-ing layer 19 is formed thereover except on the sensor areas l. mis light shielding layer 19 is formed of, for example, an aluminium layer.
In the case where the light shielding layer l9 is made as a conductive layer as set forth just above, the light shielding layer 19 is coated on the insulating layer 5 formed on the respective electrode9 thereL~
to cover the same.
As described above, according to the solid state image sensor Or the invetion, the sensor electrode 18 of each of the sensor areas 1 and the control electrode 17 of the corresponding overflow control region 8 are electrically connected. I~der - llZ54Zl such a condition that the common volta6e is applied to both tlle electro~es 17 and 18, a difference is n!ade between the minimum potentials in the sensor area 1 and the overrlow control region 8 ( in the case of the illustrated example, the minimurr. potential is generated on the surrace thereor in ~hich the minimum potential corresponds to the surface potential), and this potential difference is varied in res~onse to the applied voltage. In the above example, the surrace impurity con-centration of the sensor area 1 is selected to be as that of the substrate 4 and the surface impurity concentration ot the overrlow control region 8 is selec~ed to be higher than that of the sensor area 1. ~ ff~is case, the respective surface potentials 4~ s and ~gc in the sensor area 1 and the control regionw~th respect to the calarDn applied volta~e to the sensor and control electroc'es 18 and 17 i.e. applied voltage ~(s to the terminal t5 at the time when the thickness of the respective insulating layers 5 oi the sensor area 1 and the overflow control region 8 are selected as 3000 A, the surface impurity concentration of the sensor area 1 is selected as 5 x 1 014clr. 3 and that of the control region 8 is selected as 5 x 1015cm 3, and is made such t~at the difference betwe~
the potentials Y s and ~ c becomes greater as the applied vo1tage ~ 5 increases,as shown by curves 20 and 21 in the graph of Fig. 5.
In the abo~e example, the surface impurity concentrations of the sensor area 1 and the control region 8 are selected to cause a potential diffe~ence therebetween, but in some case it is possible that the sensor area 1 and the control region 8 h3~e the same surface iTrpurity c~-centration~ or are made diffe~lt, in ~ich case the thicknesses of the insula~
ing layers beneath t'le electr~s 18 and 17 of t~e sen50r area 1 and region 8 are made different ~lereby the thickness of the insulating layer in the sensor area 1 is selected smaller than that of the control region 8.
\~'ith the above construction, as ~ill be described later, :~lZ5~Zi the difference ( Ys~ Yc ) between the surface potentials at the over~low control region 8 and the sensor areas 1 is varied in magnitude, namely the height of the barrier between the sensor area 1 by the control region 8 and the overflow drain region 9 is varied by the magnitude Or the applied voltage SZ~ s to the terminal tS to control the overflow amount of the carrier from the sensor area 1.
For the sake of convenience of the later explanation, as shown in Fig. 2, the sensor areas 1 on each of the horizontal line are taken as sequentially S1, S2, S3, . ..., the transfer regions 11 of the corresponding vertical shift registers 2 are taken as T1 T2, T3, . ., the electrodes of every other transfer region or T1, T3, T5 .. are cronly connected to the terminal t~j and the electrodes of remaining every other transfer region or T2, T4, T6 are c~nly oor~ected to the terminal t2, respectively.
The operation of the solid state image sensor according to the present invention will be now described. D~ing the vertica:L
blanlcing interva1 the signal charges developed ~n response to the li~ht a~t received by the senso~ areas 1 are transferred to the corresponding transfer region 11 of the vertical shift register 2 (which will be hereinafter referred to as a read-out) . ~he terminals tr1 and tr2 f the vertical shift register 2 are supplied with 2-phase clock pulses g~ v1 and ~ v2~ which are shown in Figs. 6A and 6B, to sequentially transfer the signal charge to an adjacent tran~fer region in one direction during the horizontal blanking interval and hence to transfer the signal charge at every one horizontal line to the hori-zontal shift register 3 shown in Fig 1, and the signal at every horizontal line is read out from the terminal t during the horizontal scann~ng interval.
Figs. 7 to 9 are minimum potential diagrams at the res-pective regions of Fig. 3. In the diagrams, the respective minimum B
11;~5~Zl f polentials at the overîlow drain region 9, orerflow control region 81 sensor area 1, transfer gate 10 and storage region 13B are p at 5~ d~ ~ c' ~ s' ~3g and ~j6b~ and the pDlentials at the respective applied voltages are shown at the corresponding marks each with a surfix. Fig. 7 shows the light receiving and storage %~de. Under this mode the terminal tS is supplied with such a voltage that a deep well oî the potential is formed in the sensor area 1 i.e. the positive high voltage 9~ s At time tc, Or the vertical blanking interval corresponding to the beginning of an odd field interval, the ~roltages ~v1 and ~v2 ap?lied t-~ the termin~s t tS2 of the vertical shift register 2 are selected as predetermined positive voltages as shown in Figs. 6A and 6B. Under such oorlditio~
the voltage ~S5 applied to the terminal ts is lowered as shown in Fig. 6CI and Fig. 8 8}ws the Tllillil~ p~tential, the well Or the potential in the sensor area 1 is made sufficiently shal1c~w as a potential ~;s1 and the well of the potential in the storage region of the transfer region 11 corresponding to the sensor area 1 is made suf-ficiently deep as a potential Yb2~ As a result Or this, the signal charges (carriers) generated and stDred in the respective sensor areas S1~ S2, S3 --- in response to the amount Or received li6ht are trans-ferred Dr read out to the stDrage regions of the transfer regions T1, T2, T3, --- respectively as shown by an arrow b in Fig~ 8.
Next, during the vertical blanking interval while, for example, the ~oltage 51~' v2 applied to the terminal t2 is kept at the above predeter-mined positive Yoltage, the voltage ~ v1 applied to the terminal t is lowered to, for example, OV as shown in Figs. 6A and 6B .
Thus, the respective charges on every other transfer regions T1, T3, T5 --- are transferred to the remaining every other transfer regions T2, T4, T6 ~~~ and hence the charges on t~o transfer regions are added with each other. That is, the signal charges on the 11~Z54Zl sensor areas S1 ~ S3, S5 --- are superimposed on the adjacent sensor areas S2, S4~ S6~ --- re5pectively. The charges are transferred to the horizontal shift register during tihe vertic~l and h~rizontal blanking intervals as usual, but in the present invention, especially, ganna correction is carried out at a suitable nu~er of selected h~rizontal blanking intervals. In Fig 6, a pulse PT and pLllses in the hori-zontal blanking intervals,~are used for the above charge transfer.
Capplied to terminals tl and t2 In Fig. 6, since the timing of the pulses is shown schematically, the length Or the vertical blanking intervals and so on are not so correct.
In other words, the voltages applied to the terminals tr1 and tr~
during the horizontal blanking interval are both low, for example, OV, the potential barrier ~0 g at the gate region between each of the transfer regions T1~ T2, T3, --- and each of the sensor areas .S1~ S2, S3, --- is relatively high as at S~? g1 in Fig. 9, at respective times t1~ t2, t3. --- in the horizontal blanking interval the terminal ts is supplied with voltages ~ s1~ ~Zi s2~ ~i s3 ~~~ which are gr.~A11y raised in this order or SZ~ s1 < ~s2 < ~ s3 ~-- as shown in Fig. 6C, the potentials ~Ds1 ' yS2~ ~53' --- in the sensor areas 51 J S2, S3, --- are reduced ~s shown in Fig. 9, and also the potentials in the overîlow control re~ion 8 beoc~ Y~ c2 and ~)c3 as shown in Fig. 9. In this case. as described in con-nection with Fig. 5, as the applied voltage is raised, the potential difrerence between the sensor area and the overflow control region i.e. the potential barrier, is raised. As a result, the amount Or the o~lerflow is reduced. This will be now described in detail for t;~e ~ case that, for example, a light with the intensity of I4 is incident with reference to Figs. 9 and 10 . In the case that the light o~ I4 is incident~ at first charge wlbic~h is m~re than a charge anDunt q4 as determined by the di~rerence between the potential L~ s4 in the sensor area when the voltage ~ 5~ is applied to the terminal tS and the llZ~421 potential y7 c4 in the overflow control region are transrerred or drained out to the overrlow drain region, and nence the amount Or stored char~e in the sensor area is saturated at q4. Next, at the time t1 in the selected horizontal blanking interval, the terminal t1 is supplied with the relatively low voltage plS s1 ' so that charge is IlDre than a charge amount q1 determined by the difference between the potential ~jDs1 Or ~e s~nsor area and ~at of y c1 of the overflow control regionis trans-ferred to the overflow drain regi~n. The voltage applied to the term~nal tS
becares that of ~s4 again, so that in response to the light intensity of I4 a charge is stored in a sensor area which is determined by the difference between the potential y54 of the sensor area and that of,~;Dc4 of the overrlow control region. Superrluous charges ~f m~re than the charge amount q4 are transferred to the overflow drain region.
Next, at the time t2 in another selected horizontal blanking interval, the terminal ts is supplied with the voltage S~!~ s2 ~ch is higher than the fo~rer voltage 5Z~ s1 ' so that charge is increased b~ a~t q2 determi~
by the difference between the potential ~DS2 ~f the sensor area and that 4D c2 Or the overflow control region is transferred to the overflo~Y
drain region. Thereafter, the terminal tS is supplied with the voltage 9~ s4 again- and the ~harges are stored. Then, at the t~lre t3 in a ~ird selected horizontal blanking interval, the terminal ts is supplied with the voltage ~ s3 higher than that of .0 s2 and hence that ~iharge n~re than the charge amount q3 is drained out. Thereatter, the terminal tS
is supplied with the voltage ~ s4' so that charges are stored in res-ponse to the incident light. Then, the charges are read out a- the time t4 in the ~rertical blanking inter~al. When the image sensor receives light with the intension l,which has the relation of Io < 11 ~ I2 ~ I3 < 14~ the charge amount q stored in the sensor area 1 at the times to~ tl ~ t2~ t3 and t4 is now considered. As sh~wn in Fig.
10, charges more than the charges q1 ~ q2, q3 and q4 in the sensor B
--` 11;2~
area 1 determined by the potential ~ - ~ at the times tl, t2, t3 and t4 are overflowed and drained out, so that the charge amounts corresponding to the light with the intensity 1 is expressed by a power function curve as shown in Fig. 11 i.e. gamma correction is carried. In Figs. 10 and 11, when a light with the intensity of Io which is lower than the intensity OM is incident, the charge amount stored in the sensor area is shown by a line ~1 When a light with the intensity of I
between the intensities IOM and IlM is incident, the charge amount stored in the sensor area is shown by a line ~2. The other lines ~3, ~4 --- show the similar charge amounts stored in the sensor areas.
The gamma correction can be carried out similarly in the following even field by the similar operation. In an even - field, as shown in Fig. 6, after the reading out from the r~9pective sensor areas Sl, S2, S3 --- corresponding to the transfer regions Tl, T2, T3, --- of the vertical shift register 2 in the vertical blanking interval corresponding to the beginning of the even field, contrary to the case of the above 2~0 odd field, under the voltage at the terminal tl which is kept at a predetermined positive voltage, the terminal t2 is supplied with, for example, OV and the charges in the sensor areas S2, S3 S4, --- are added to those of the ad~acent sensor areas Sl, S2, S3, --- which combination is selected to be different from that in the odd field. That is,in the even field by the combinations of the sensor areas Sl and S2, S3 and S4, S5 and S6, ---, a one picture element signal is provided, while in the odd field by the other combinations of the sensor S2 and S3, S~ and S5, S6 and S7 --- a one picture element signal is provided, respectively. By the above manner, one picture (one frame) is formed of 2 fields to provide interlacing effect.
ilZ5~1 With the above construction, iE it is desired that its sensibility is adjusted, the width of the overflow control region 8 is selected sufficiently narr~w and the bias in the overflow drain region 9 is - 14a -made deep, as shown in Fig. 12, so that its potential e~ects the over-flow control region 8 and hence to lower the barrier thereof and to escape the carrier in the sensor area 1 to the overrlow drain region 9. That is, ~hen a large bias is applied t~ the overflow drain region 9, the signal charge generated in the sensor area 1 is transferred to the overflow drain region 9 and hence is not stored in the sensor area 1. Accordingly, the time interval for storing the carrier can be shortened in accordance with the amount Or received light As described a~bove, according to the present invention, without providing an independent electrode on the overflo~ control region, gamma oorrection can be performed. Such defects ~Duld reguire that the electrode construction beoc~es ocmplicated, the manu-facturing thereof becomes troublesome, the reliability is lowered and the yield is lowered can be avoided.
Further, with the invention constructed as above, since the charges in all the sensor areas Sl, S2, S3 --- are read out at the be-ginning of each of the respective fields, no problem on a res~dual image appears. That is, if the charges are read out from every other sensor area in each of the fields as in the prior art, as the light is received by the sensor areas even in a field interval within ~vhich the remaining every other sensor area is read out, the light is received in two fields. Thus, there occurs a problem of a resi-dual image, but such a problem is dissolved by the present invention as set forth above.
In the above example of the invention, the sensor electrode is formed common and the signal charges in the respective sensor areas are read out in each of the fields. However~ it is also possible in sca~e cases that the sensor ele~trode connection is divided with the combinations of the sensor areas S1 ~ S3, S5 --- and S2, S4, S6, ---at every other horizontal line, and every other sensor area is read out in each of the fields.
5~Zl The above description is given on a single prererred example of the present invention, but it will be apparent that manv modifications and variations could be effected by one skilled in the art without departing from the spirits or scope Or the novel concepts Or the present invention, ~ " .
in Fi~. 2, respectively. In the rigures. 4 designates a semi-conductor substra-e,such as a silicon substrate, havinp P-type cond~ctivity,on the surrace Or hich there is coated an insulating -5a-~3 11254Zl layer 5Jsuch as a SiO2 layer. In the example illustrated in ~he figures, the vertical shift register 2 is formed as a buried channel .
To this end, a region 6, having an N-type conductivity which is ditrerent from the su~strate 4,is formed in the substrate 4 an~l the major sur-face ther~of is in a stripe or ~and shape along the pæ t which forlr the shift register 2. A cha~nel stopper region 7,having the same conductivity as the substrate 4 and having high i~purity concent-ration,is formed in the substrate 4 such that it separates the adjacent sensor areas 1 and shift register 2 as shown in Fig. 2 and faoes the major surface 4a. An overflow control region 8, h~ving the conductivity which is same as that of the substrate 4,is formed in the substrate 4, and an overflow drain region 9, having a N-type conductivit~ of high impurity concentration different from the substrate 4, is formed in the latter adjacent each of the sensor areas 1 through the overflow control region 8 and disposed to faoe the major surfaoe 4a. Also, a gate region 1(~ havin~ ne ~-type conductivitv,is formed in the substrate 4 between each of the sensor areas 1 and the shift registers 2 corresponding thereto.
Each of the shift registers 2 is formed of a transfer region 11 disposed in oorrespondence with each of the sensor areas 1 arranged on a vertical line. In the illustrated example, the vertical shift register 2 is formed as a 2-phase clock type. In this case, each of the transter re~ions 11 consists Or~ for example, a part including a relatively thin insulating layer 5A and a part including a thick insula-ting layer 5B. On the insulating layers 5A and 5B there are formed electrodes 12A and 12B to form a so-called transfer gate 13A and a sborage region 1 3B, respectively. Both the electrodes 1 2A and 1 2B in the transfer re~ion 11 are electrically connected.
Jn the example, as shown in Fig. 4, in order to provide a difrerence between the depths Or potentials in the transfer gate 1 3A
:llZ5~Zl and strage region 13B Or the vertical shift register Z~ the insulating layers 5 and 5B beneath the electr~des 12A and lZB are made o different t,hickness for each other. H~ever, it is also possible t-~at the potentials can be made of dif~er~ltdepth by utilizing the difrerence of ilrçNrity bulk concentrations instead of utilizing the diffe~ence between the thicknesses of the insulating layers. In this latter case, the insulating layers 5A an~ 5B beneath the transter and st~e ele-ctrodes 1 2A an~ 1 2B are equal. but a shallow region ha~ring P-type conductivity is formed beneath the transfer electrode 1 2A This P-type region car. be formed by, for example, carrying out ion implantation selectively.
The gate region 1 0,between each Or the sensor areas 1 and the corresponding vertical shift register 2, which has, for example, the same conductivity as the substrate 4. is formed with a region 14 in the substrate 4 and has an ~urity concentration higher than that of the substrate 4 and faces the major surface 4a thereof. E~xn the upper surface of the region 14 ext~ds the insu-lating layer 5, ror example, insulating layer 5B on which a gate ele-ctro~e 15 is coated. The gate electrode 15 of the gate region 10 corresponding to each of the sensor areas 1 and the electrodes 1 3A
and 1 3B o~ each of the transfer regions 11 in the vertical shift register 2, are a~y form~d as ~dwwn in Fig. 2 by a dotted line a, or ele-ctrically connected so as to be supplied with a ca~n v~ltage. In this case. even i~ the same voltage is applied to the respective electrodes of the gate region 10 and the transfer region 11, the impurity concent-rationC in the reE~ions 10 and 11 or the thicknesses of the insulating layers,are so selected that the minimum potentials in the respective regions are always shallow in the gate region. From every other transfer region l1, which are connected together and the connection le~ out are termir~s trl and tr2.
11~5~2~
rhe o~erflow control region 8 is- for example~ of the same conductivity as the substrate 4 and is formed or a region 16 which is formed in the substrate 4~ and is ~ her th~n the latter in ~l!purity concen-tration and faces the major surface 4a. A control electrode 17 is formed thro~-gh the insulating layer 5 on the region 16.
The sensor area 1 is formed by forming a sensor electrode 18 on the insulating layer 5 and through which light passes. me sensor electrode 18 and the control electrode 17 of the corresponding overflow control region 8 are formed of a cc~non continuous transparent ele-ctrode or connected electrically and to ~ich a c~n voltage is applied through a terminal tS~
The respective regions 6, 7, 9, 14 and 16 can be formed by a well known technique such as the selective diff~lsion method, ion implantation method or the like. The respective electrodes 15, 1 2A
and 12B are formed by sequentially depositing polycrystalline silicon layers, which are made low in resistance by an impurity doped thereinto, ~y a chemic 1 vapour deposition meth~d. me insulating layers are formed by o~idi~.ing the surfaces ot the layers and hence the transparent electroce, ~hich form the sensor electrode 18 and overflaw control electrode 17, is formed all over the insulating lay-er 5 A light shield-ing layer 19 is formed thereover except on the sensor areas l. mis light shielding layer 19 is formed of, for example, an aluminium layer.
In the case where the light shielding layer l9 is made as a conductive layer as set forth just above, the light shielding layer 19 is coated on the insulating layer 5 formed on the respective electrode9 thereL~
to cover the same.
As described above, according to the solid state image sensor Or the invetion, the sensor electrode 18 of each of the sensor areas 1 and the control electrode 17 of the corresponding overflow control region 8 are electrically connected. I~der - llZ54Zl such a condition that the common volta6e is applied to both tlle electro~es 17 and 18, a difference is n!ade between the minimum potentials in the sensor area 1 and the overrlow control region 8 ( in the case of the illustrated example, the minimurr. potential is generated on the surrace thereor in ~hich the minimum potential corresponds to the surface potential), and this potential difference is varied in res~onse to the applied voltage. In the above example, the surrace impurity con-centration of the sensor area 1 is selected to be as that of the substrate 4 and the surface impurity concentration ot the overrlow control region 8 is selec~ed to be higher than that of the sensor area 1. ~ ff~is case, the respective surface potentials 4~ s and ~gc in the sensor area 1 and the control regionw~th respect to the calarDn applied volta~e to the sensor and control electroc'es 18 and 17 i.e. applied voltage ~(s to the terminal t5 at the time when the thickness of the respective insulating layers 5 oi the sensor area 1 and the overflow control region 8 are selected as 3000 A, the surface impurity concentration of the sensor area 1 is selected as 5 x 1 014clr. 3 and that of the control region 8 is selected as 5 x 1015cm 3, and is made such t~at the difference betwe~
the potentials Y s and ~ c becomes greater as the applied vo1tage ~ 5 increases,as shown by curves 20 and 21 in the graph of Fig. 5.
In the abo~e example, the surface impurity concentrations of the sensor area 1 and the control region 8 are selected to cause a potential diffe~ence therebetween, but in some case it is possible that the sensor area 1 and the control region 8 h3~e the same surface iTrpurity c~-centration~ or are made diffe~lt, in ~ich case the thicknesses of the insula~
ing layers beneath t'le electr~s 18 and 17 of t~e sen50r area 1 and region 8 are made different ~lereby the thickness of the insulating layer in the sensor area 1 is selected smaller than that of the control region 8.
\~'ith the above construction, as ~ill be described later, :~lZ5~Zi the difference ( Ys~ Yc ) between the surface potentials at the over~low control region 8 and the sensor areas 1 is varied in magnitude, namely the height of the barrier between the sensor area 1 by the control region 8 and the overflow drain region 9 is varied by the magnitude Or the applied voltage SZ~ s to the terminal tS to control the overflow amount of the carrier from the sensor area 1.
For the sake of convenience of the later explanation, as shown in Fig. 2, the sensor areas 1 on each of the horizontal line are taken as sequentially S1, S2, S3, . ..., the transfer regions 11 of the corresponding vertical shift registers 2 are taken as T1 T2, T3, . ., the electrodes of every other transfer region or T1, T3, T5 .. are cronly connected to the terminal t~j and the electrodes of remaining every other transfer region or T2, T4, T6 are c~nly oor~ected to the terminal t2, respectively.
The operation of the solid state image sensor according to the present invention will be now described. D~ing the vertica:L
blanlcing interva1 the signal charges developed ~n response to the li~ht a~t received by the senso~ areas 1 are transferred to the corresponding transfer region 11 of the vertical shift register 2 (which will be hereinafter referred to as a read-out) . ~he terminals tr1 and tr2 f the vertical shift register 2 are supplied with 2-phase clock pulses g~ v1 and ~ v2~ which are shown in Figs. 6A and 6B, to sequentially transfer the signal charge to an adjacent tran~fer region in one direction during the horizontal blanking interval and hence to transfer the signal charge at every one horizontal line to the hori-zontal shift register 3 shown in Fig 1, and the signal at every horizontal line is read out from the terminal t during the horizontal scann~ng interval.
Figs. 7 to 9 are minimum potential diagrams at the res-pective regions of Fig. 3. In the diagrams, the respective minimum B
11;~5~Zl f polentials at the overîlow drain region 9, orerflow control region 81 sensor area 1, transfer gate 10 and storage region 13B are p at 5~ d~ ~ c' ~ s' ~3g and ~j6b~ and the pDlentials at the respective applied voltages are shown at the corresponding marks each with a surfix. Fig. 7 shows the light receiving and storage %~de. Under this mode the terminal tS is supplied with such a voltage that a deep well oî the potential is formed in the sensor area 1 i.e. the positive high voltage 9~ s At time tc, Or the vertical blanking interval corresponding to the beginning of an odd field interval, the ~roltages ~v1 and ~v2 ap?lied t-~ the termin~s t tS2 of the vertical shift register 2 are selected as predetermined positive voltages as shown in Figs. 6A and 6B. Under such oorlditio~
the voltage ~S5 applied to the terminal ts is lowered as shown in Fig. 6CI and Fig. 8 8}ws the Tllillil~ p~tential, the well Or the potential in the sensor area 1 is made sufficiently shal1c~w as a potential ~;s1 and the well of the potential in the storage region of the transfer region 11 corresponding to the sensor area 1 is made suf-ficiently deep as a potential Yb2~ As a result Or this, the signal charges (carriers) generated and stDred in the respective sensor areas S1~ S2, S3 --- in response to the amount Or received li6ht are trans-ferred Dr read out to the stDrage regions of the transfer regions T1, T2, T3, --- respectively as shown by an arrow b in Fig~ 8.
Next, during the vertical blanking interval while, for example, the ~oltage 51~' v2 applied to the terminal t2 is kept at the above predeter-mined positive Yoltage, the voltage ~ v1 applied to the terminal t is lowered to, for example, OV as shown in Figs. 6A and 6B .
Thus, the respective charges on every other transfer regions T1, T3, T5 --- are transferred to the remaining every other transfer regions T2, T4, T6 ~~~ and hence the charges on t~o transfer regions are added with each other. That is, the signal charges on the 11~Z54Zl sensor areas S1 ~ S3, S5 --- are superimposed on the adjacent sensor areas S2, S4~ S6~ --- re5pectively. The charges are transferred to the horizontal shift register during tihe vertic~l and h~rizontal blanking intervals as usual, but in the present invention, especially, ganna correction is carried out at a suitable nu~er of selected h~rizontal blanking intervals. In Fig 6, a pulse PT and pLllses in the hori-zontal blanking intervals,~are used for the above charge transfer.
Capplied to terminals tl and t2 In Fig. 6, since the timing of the pulses is shown schematically, the length Or the vertical blanking intervals and so on are not so correct.
In other words, the voltages applied to the terminals tr1 and tr~
during the horizontal blanking interval are both low, for example, OV, the potential barrier ~0 g at the gate region between each of the transfer regions T1~ T2, T3, --- and each of the sensor areas .S1~ S2, S3, --- is relatively high as at S~? g1 in Fig. 9, at respective times t1~ t2, t3. --- in the horizontal blanking interval the terminal ts is supplied with voltages ~ s1~ ~Zi s2~ ~i s3 ~~~ which are gr.~A11y raised in this order or SZ~ s1 < ~s2 < ~ s3 ~-- as shown in Fig. 6C, the potentials ~Ds1 ' yS2~ ~53' --- in the sensor areas 51 J S2, S3, --- are reduced ~s shown in Fig. 9, and also the potentials in the overîlow control re~ion 8 beoc~ Y~ c2 and ~)c3 as shown in Fig. 9. In this case. as described in con-nection with Fig. 5, as the applied voltage is raised, the potential difrerence between the sensor area and the overflow control region i.e. the potential barrier, is raised. As a result, the amount Or the o~lerflow is reduced. This will be now described in detail for t;~e ~ case that, for example, a light with the intensity of I4 is incident with reference to Figs. 9 and 10 . In the case that the light o~ I4 is incident~ at first charge wlbic~h is m~re than a charge anDunt q4 as determined by the di~rerence between the potential L~ s4 in the sensor area when the voltage ~ 5~ is applied to the terminal tS and the llZ~421 potential y7 c4 in the overflow control region are transrerred or drained out to the overrlow drain region, and nence the amount Or stored char~e in the sensor area is saturated at q4. Next, at the time t1 in the selected horizontal blanking interval, the terminal t1 is supplied with the relatively low voltage plS s1 ' so that charge is IlDre than a charge amount q1 determined by the difference between the potential ~jDs1 Or ~e s~nsor area and ~at of y c1 of the overflow control regionis trans-ferred to the overflow drain regi~n. The voltage applied to the term~nal tS
becares that of ~s4 again, so that in response to the light intensity of I4 a charge is stored in a sensor area which is determined by the difference between the potential y54 of the sensor area and that of,~;Dc4 of the overrlow control region. Superrluous charges ~f m~re than the charge amount q4 are transferred to the overflow drain region.
Next, at the time t2 in another selected horizontal blanking interval, the terminal ts is supplied with the voltage S~!~ s2 ~ch is higher than the fo~rer voltage 5Z~ s1 ' so that charge is increased b~ a~t q2 determi~
by the difference between the potential ~DS2 ~f the sensor area and that 4D c2 Or the overflow control region is transferred to the overflo~Y
drain region. Thereafter, the terminal tS is supplied with the voltage 9~ s4 again- and the ~harges are stored. Then, at the t~lre t3 in a ~ird selected horizontal blanking interval, the terminal ts is supplied with the voltage ~ s3 higher than that of .0 s2 and hence that ~iharge n~re than the charge amount q3 is drained out. Thereatter, the terminal tS
is supplied with the voltage ~ s4' so that charges are stored in res-ponse to the incident light. Then, the charges are read out a- the time t4 in the ~rertical blanking inter~al. When the image sensor receives light with the intension l,which has the relation of Io < 11 ~ I2 ~ I3 < 14~ the charge amount q stored in the sensor area 1 at the times to~ tl ~ t2~ t3 and t4 is now considered. As sh~wn in Fig.
10, charges more than the charges q1 ~ q2, q3 and q4 in the sensor B
--` 11;2~
area 1 determined by the potential ~ - ~ at the times tl, t2, t3 and t4 are overflowed and drained out, so that the charge amounts corresponding to the light with the intensity 1 is expressed by a power function curve as shown in Fig. 11 i.e. gamma correction is carried. In Figs. 10 and 11, when a light with the intensity of Io which is lower than the intensity OM is incident, the charge amount stored in the sensor area is shown by a line ~1 When a light with the intensity of I
between the intensities IOM and IlM is incident, the charge amount stored in the sensor area is shown by a line ~2. The other lines ~3, ~4 --- show the similar charge amounts stored in the sensor areas.
The gamma correction can be carried out similarly in the following even field by the similar operation. In an even - field, as shown in Fig. 6, after the reading out from the r~9pective sensor areas Sl, S2, S3 --- corresponding to the transfer regions Tl, T2, T3, --- of the vertical shift register 2 in the vertical blanking interval corresponding to the beginning of the even field, contrary to the case of the above 2~0 odd field, under the voltage at the terminal tl which is kept at a predetermined positive voltage, the terminal t2 is supplied with, for example, OV and the charges in the sensor areas S2, S3 S4, --- are added to those of the ad~acent sensor areas Sl, S2, S3, --- which combination is selected to be different from that in the odd field. That is,in the even field by the combinations of the sensor areas Sl and S2, S3 and S4, S5 and S6, ---, a one picture element signal is provided, while in the odd field by the other combinations of the sensor S2 and S3, S~ and S5, S6 and S7 --- a one picture element signal is provided, respectively. By the above manner, one picture (one frame) is formed of 2 fields to provide interlacing effect.
ilZ5~1 With the above construction, iE it is desired that its sensibility is adjusted, the width of the overflow control region 8 is selected sufficiently narr~w and the bias in the overflow drain region 9 is - 14a -made deep, as shown in Fig. 12, so that its potential e~ects the over-flow control region 8 and hence to lower the barrier thereof and to escape the carrier in the sensor area 1 to the overrlow drain region 9. That is, ~hen a large bias is applied t~ the overflow drain region 9, the signal charge generated in the sensor area 1 is transferred to the overflow drain region 9 and hence is not stored in the sensor area 1. Accordingly, the time interval for storing the carrier can be shortened in accordance with the amount Or received light As described a~bove, according to the present invention, without providing an independent electrode on the overflo~ control region, gamma oorrection can be performed. Such defects ~Duld reguire that the electrode construction beoc~es ocmplicated, the manu-facturing thereof becomes troublesome, the reliability is lowered and the yield is lowered can be avoided.
Further, with the invention constructed as above, since the charges in all the sensor areas Sl, S2, S3 --- are read out at the be-ginning of each of the respective fields, no problem on a res~dual image appears. That is, if the charges are read out from every other sensor area in each of the fields as in the prior art, as the light is received by the sensor areas even in a field interval within ~vhich the remaining every other sensor area is read out, the light is received in two fields. Thus, there occurs a problem of a resi-dual image, but such a problem is dissolved by the present invention as set forth above.
In the above example of the invention, the sensor electrode is formed common and the signal charges in the respective sensor areas are read out in each of the fields. However~ it is also possible in sca~e cases that the sensor ele~trode connection is divided with the combinations of the sensor areas S1 ~ S3, S5 --- and S2, S4, S6, ---at every other horizontal line, and every other sensor area is read out in each of the fields.
5~Zl The above description is given on a single prererred example of the present invention, but it will be apparent that manv modifications and variations could be effected by one skilled in the art without departing from the spirits or scope Or the novel concepts Or the present invention, ~ " .
Claims (14)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A solid state image sensor comprising:
a) a semiconductor substrate, b) a plurality of sensor regions formed of portions of said substrate arranged in row and column directions, which are able to store signal charges of predetermined amount during a predetermined period, c) a shift register formed of a portion of said substrate associated with each row of said sensor regions, d) an overflow drain formed of a portion of said substrate associated with each row of said sensor regions at the opposite side of said row of said sensor regions with respect to said shift register, e) first means to form a first potential barrier for signal charges between said sensor regions and said shift register during predetermined intervals, said barrier sequentially increasing in said predetermined period, f) second means to form a second potential barrier for signal charges between said sensor regions and said overflow drain region, said second potential barrier being lower than said first potential barrier during said predetermined intervals, and to form potential wells at said sensor regions to store stored in said potential well being defined by said second potential barrier and said potential well, and, g) third means to form said second potential barrier and potential well such that the said predeter-mined amount of signal charges to be stored,in said sensor regions, are increased at timings at inter-mittently selected intervals from said predeter-mined intervals.
a) a semiconductor substrate, b) a plurality of sensor regions formed of portions of said substrate arranged in row and column directions, which are able to store signal charges of predetermined amount during a predetermined period, c) a shift register formed of a portion of said substrate associated with each row of said sensor regions, d) an overflow drain formed of a portion of said substrate associated with each row of said sensor regions at the opposite side of said row of said sensor regions with respect to said shift register, e) first means to form a first potential barrier for signal charges between said sensor regions and said shift register during predetermined intervals, said barrier sequentially increasing in said predetermined period, f) second means to form a second potential barrier for signal charges between said sensor regions and said overflow drain region, said second potential barrier being lower than said first potential barrier during said predetermined intervals, and to form potential wells at said sensor regions to store stored in said potential well being defined by said second potential barrier and said potential well, and, g) third means to form said second potential barrier and potential well such that the said predeter-mined amount of signal charges to be stored,in said sensor regions, are increased at timings at inter-mittently selected intervals from said predeter-mined intervals.
Claim 2 : A solid state image sensor according to claim 1, in which said first means includes an electrode electrically insulated from said substrate and provided over a portion of a surface of said substrate between said sensor region and said shift register, and a predetermined voltage applied thereto.
Claim 3 : A solid state image sensor according to claim 1, in which said second means includes an electrode electrically insulated from said substrate and provided over said substrate and a portion of a surface of said substrate between said sensor regions and said overflow drain region and a predetermined voltage applied thereto.
Claim 4 : A solid state image sensor according to claim 1, in which said predetermined period corresponds to a vertical scanning interval of television signal.
Claim 5 : A solid state image sensor according to claim 1, in which said predetermined interval corresponds to a horizontal blanking interval of television signal.
Claim 6 : A solid state image sensor according to claim 2, in which said electrode is an extension of an electrode of said shift register.
Claim 7 : A solid state image sensor according to claim 3, in which the surface impurity concentrations of said substrate at said sensor region and said overflow control region are different.
Claim 8 : A solid state image sensor according to claim 3, in which an insulating layer in provided between said surface of said substrate and said electrode, and the thickness of said insulating layer at said sensor region and said overflow control region are different from each other.
Claim 9 : A solid state image sensor according to claim 1, further comprising forth means to apply a predeter-mined voltage to said overflow drain so as not to form said second potential barrier.
Claim 10: A solid state image sensor comprising;
a) a semiconductor substrate, b) a plurality of picture elements formed of portions of said substrate arranged in row and column directions, which store signal charges in a pre-determined period, c) a shift register formed of a portion of said substrate associated with each row of said picture elements through transfer gate regions, d) an overflow drain region formed of a portion of said substrate associated with each row of said picture elements at the opposite side of said row of picture elements with respect to said shift register and separated from said row by an overflow control region.
e) a transfer electrode for said shift register electrically insulated from said substrate and provided over a portion of said shift register and said transfer gate region, f) a sensor electrode electrically insulated from said substrate and said transfer electrode provided over said picture elements and said overflow control regions, said transfer electrode having a voltage applied thereto to form a potential barrier at said transfer gate region during a predetermined interval, said sensor electrode having predetermined voltages applied thereto at a plurality of timings in intermittently selected intervals from said predetermined interval each of said timings being in each of said selected intervals, means being provided to cause a potential difference between said picture element and said overflow control region which determines an amount of signal charge to be stored at said picture element by the application of said predetermined voltage, said predetermined voltages being selected such that the amount of signal charges to be stored at said picture element by the first voltage at an earlier timing is smaller than the amount of signal charges to be stored at said picture element at a later timing, and said sensor electrode having a voltage applied thereto to cause a potential well at said picture element to store signal charges during the rest of said timings in said predetermined period,
a) a semiconductor substrate, b) a plurality of picture elements formed of portions of said substrate arranged in row and column directions, which store signal charges in a pre-determined period, c) a shift register formed of a portion of said substrate associated with each row of said picture elements through transfer gate regions, d) an overflow drain region formed of a portion of said substrate associated with each row of said picture elements at the opposite side of said row of picture elements with respect to said shift register and separated from said row by an overflow control region.
e) a transfer electrode for said shift register electrically insulated from said substrate and provided over a portion of said shift register and said transfer gate region, f) a sensor electrode electrically insulated from said substrate and said transfer electrode provided over said picture elements and said overflow control regions, said transfer electrode having a voltage applied thereto to form a potential barrier at said transfer gate region during a predetermined interval, said sensor electrode having predetermined voltages applied thereto at a plurality of timings in intermittently selected intervals from said predetermined interval each of said timings being in each of said selected intervals, means being provided to cause a potential difference between said picture element and said overflow control region which determines an amount of signal charge to be stored at said picture element by the application of said predetermined voltage, said predetermined voltages being selected such that the amount of signal charges to be stored at said picture element by the first voltage at an earlier timing is smaller than the amount of signal charges to be stored at said picture element at a later timing, and said sensor electrode having a voltage applied thereto to cause a potential well at said picture element to store signal charges during the rest of said timings in said predetermined period,
Claim 11: A solid state image sensor according to claim 10, in which said means is a difference of surface impurity concentration of said substrate at said picture element and said overflow control region.
Claim 12: A solid state image sensor according to claim 10, in which said means is a difference of thickness of an insulating layer interposed between a surface of said substrate and said sensor electrode at said picture element and at said overflow control region.
Claim 13: A solid state image sensor according to claim 10, in which said predetermined period corresponds to a vertical scanning interval of television signal.
Claim 14: A solid state image sensor according to claim 10, in which said predetermined interval corresponds to a horizontal blanking interval of television signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP126885/77 | 1977-09-29 | ||
| JP12688577A JPS5451318A (en) | 1977-09-29 | 1977-09-29 | Solid pickup unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1125421A true CA1125421A (en) | 1982-06-08 |
Family
ID=14946246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA312,252A Expired CA1125421A (en) | 1977-09-29 | 1978-09-28 | Solid state image sensor |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5451318A (en) |
| CA (1) | CA1125421A (en) |
| DE (1) | DE2842346A1 (en) |
| FR (1) | FR2409646A1 (en) |
| GB (1) | GB2007937B (en) |
| NL (1) | NL7809866A (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55151592U (en) * | 1979-04-19 | 1980-10-31 | ||
| JPS55163882A (en) * | 1979-06-06 | 1980-12-20 | Nec Corp | System for driving charge transfer element |
| JPS55163953A (en) * | 1979-06-08 | 1980-12-20 | Nec Corp | Ccd shift register |
| JPS55163956A (en) * | 1979-06-08 | 1980-12-20 | Nec Corp | Shift register and its driving method |
| DE2939403A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | MONOLITHICALLY INTEGRATED CIRCUIT FOR LINE SCREENING |
| JPS5665578A (en) * | 1979-10-31 | 1981-06-03 | Fujitsu Ltd | Two dimensional solidstate image sensor |
| JPS5685981A (en) * | 1979-12-15 | 1981-07-13 | Sharp Corp | Solid image pickup apparatus |
| JPS56104582A (en) * | 1980-01-25 | 1981-08-20 | Toshiba Corp | Solid image pickup device |
| JPS56136086A (en) * | 1980-03-27 | 1981-10-23 | Fujitsu Ltd | Two-dimensional image pickup device |
| JPS56160081A (en) * | 1980-05-14 | 1981-12-09 | Matsushita Electronics Corp | Solid state image pickup apparatus |
| DE3173604D1 (en) * | 1981-05-19 | 1986-03-13 | Texas Instruments Inc | Infrared imaging system with infrared detector matrix, and method of imaging infrared energy |
| DE3121494A1 (en) * | 1981-05-29 | 1983-01-05 | Siemens AG, 1000 Berlin und 8000 München | ARRANGEMENT FOR THE CONTACTLESS MEASUREMENT OF ELECTRICAL CHARGE IMAGES IN ELECTRORADIOGRAPHIC RECORDING METHODS |
| DE3172696D1 (en) * | 1981-06-03 | 1985-11-28 | Texas Instruments Inc | Infrared energy detector system utilizing a charge transfer device sensor |
| JPS586682A (en) * | 1981-07-06 | 1983-01-14 | Sony Corp | Solid-state image pickup device |
| JPS5847378A (en) * | 1981-09-17 | 1983-03-19 | Canon Inc | Image pickup element |
| JPS58142570A (en) * | 1982-02-19 | 1983-08-24 | Sony Corp | Solid-state image pickup device |
| JPS60254770A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Charge transfer device |
| JPS61144874A (en) * | 1984-12-19 | 1986-07-02 | Toshiba Corp | Charge transfer device |
| NL8503243A (en) * | 1985-11-25 | 1987-06-16 | Optische Ind De Oude Delft Nv | IMAGE RECORDING DEVICE FOR DIGITAL RADIOGRAPHY. |
| JPH07107928B2 (en) * | 1986-03-25 | 1995-11-15 | ソニー株式会社 | Solid-state imaging device |
| JPH02113678A (en) * | 1988-10-21 | 1990-04-25 | Nec Corp | Solid state image pickup device |
| US5055667A (en) * | 1990-06-21 | 1991-10-08 | Loral Fairchild Corporation | Non-linear photosite response in CCD imagers |
| US5276520A (en) * | 1991-06-07 | 1994-01-04 | Eastman Kodak Company | Enhancing exposure latitude of image sensors |
| FR2687265A1 (en) * | 1993-01-08 | 1993-08-13 | Scanera Sc | Electronic image acquisition device with very high dynamic range, and method of acquiring images of very highly contrasted scenes |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654115B2 (en) * | 1974-03-29 | 1981-12-23 | ||
| US3931465A (en) * | 1975-01-13 | 1976-01-06 | Rca Corporation | Blooming control for charge coupled imager |
| JPS5937629B2 (en) * | 1975-01-30 | 1984-09-11 | ソニー株式会社 | solid-state imaging body |
| US3953733A (en) * | 1975-05-21 | 1976-04-27 | Rca Corporation | Method of operating imagers |
| JPS5846905B2 (en) * | 1975-11-10 | 1983-10-19 | ソニー株式会社 | Kotai Satsuzou Sochi |
| JPS52109825A (en) * | 1976-03-11 | 1977-09-14 | Sony Corp | Solid state pick up unit |
-
1977
- 1977-09-29 JP JP12688577A patent/JPS5451318A/en active Pending
-
1978
- 1978-09-22 FR FR7827214A patent/FR2409646A1/en active Granted
- 1978-09-28 GB GB7838523A patent/GB2007937B/en not_active Expired
- 1978-09-28 DE DE19782842346 patent/DE2842346A1/en active Granted
- 1978-09-28 CA CA312,252A patent/CA1125421A/en not_active Expired
- 1978-09-29 NL NL7809866A patent/NL7809866A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| DE2842346C2 (en) | 1987-05-14 |
| GB2007937A (en) | 1979-05-23 |
| DE2842346A1 (en) | 1979-04-12 |
| FR2409646A1 (en) | 1979-06-15 |
| JPS5451318A (en) | 1979-04-23 |
| FR2409646B1 (en) | 1983-11-18 |
| GB2007937B (en) | 1982-03-03 |
| NL7809866A (en) | 1979-04-02 |
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Legal Events
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| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 19990608 |