CA1103807A - Fibonacci code adder - Google Patents

Fibonacci code adder

Info

Publication number
CA1103807A
CA1103807A CA293,680A CA293680A CA1103807A CA 1103807 A CA1103807 A CA 1103807A CA 293680 A CA293680 A CA 293680A CA 1103807 A CA1103807 A CA 1103807A
Authority
CA
Canada
Prior art keywords
output
gate
input
inputs
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA293,680A
Other languages
English (en)
French (fr)
Inventor
Alexei P. Stakhov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Original Assignee
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova filed Critical Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Application granted granted Critical
Publication of CA1103807A publication Critical patent/CA1103807A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
CA293,680A 1976-12-22 1977-12-22 Fibonacci code adder Expired CA1103807A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SU2432391 1976-12-22
SU762432391A SU732864A1 (ru) 1976-12-22 1976-12-22 Сумматор кодов фибоначчи

Publications (1)

Publication Number Publication Date
CA1103807A true CA1103807A (en) 1981-06-23

Family

ID=20687540

Family Applications (1)

Application Number Title Priority Date Filing Date
CA293,680A Expired CA1103807A (en) 1976-12-22 1977-12-22 Fibonacci code adder

Country Status (9)

Country Link
US (1) US4159529A (cg-RX-API-DMAC10.html)
JP (1) JPS53101242A (cg-RX-API-DMAC10.html)
CA (1) CA1103807A (cg-RX-API-DMAC10.html)
DD (1) DD136317A1 (cg-RX-API-DMAC10.html)
DE (1) DE2756832A1 (cg-RX-API-DMAC10.html)
FR (1) FR2375655A1 (cg-RX-API-DMAC10.html)
GB (1) GB1565460A (cg-RX-API-DMAC10.html)
PL (1) PL109971B1 (cg-RX-API-DMAC10.html)
SU (1) SU732864A1 (cg-RX-API-DMAC10.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU840891A1 (ru) * 1978-05-15 1981-06-23 Винницкийполитехнический Институт Параллельный сумматор кодов фибоначчи
EP0754373B1 (en) * 1995-02-03 2001-06-06 Koninklijke Philips Electronics N.V. Encoding arrangement for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1) bit information words
US6934733B1 (en) * 2001-12-12 2005-08-23 Lsi Logic Corporation Optimization of adder based circuit architecture
CN112787658B (zh) * 2020-12-31 2022-12-13 卓尔智联(武汉)研究院有限公司 基于斐波那契进制的逻辑运算电路
US12511123B2 (en) * 2022-10-28 2025-12-30 Jun Zhou Fast carry-calculation oriented redundancy-tolerated fixed-point number coding for massive parallel ALU circuitry design in GPU, TPU, NPU, AI infer chip, CPU, and other computing devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1547633A (fr) * 1967-10-16 1968-11-29 Labo Cent Telecommunicat Circuit d'addition de nombres binaires provenant du codage non linéaire de signaux

Also Published As

Publication number Publication date
US4159529A (en) 1979-06-26
PL203158A1 (pl) 1978-12-18
SU732864A1 (ru) 1980-05-05
FR2375655A1 (fr) 1978-07-21
JPS53101242A (en) 1978-09-04
JPS573100B2 (cg-RX-API-DMAC10.html) 1982-01-20
PL109971B1 (en) 1980-06-30
FR2375655B1 (cg-RX-API-DMAC10.html) 1980-08-22
GB1565460A (en) 1980-04-23
DD136317A1 (de) 1979-06-27
DE2756832A1 (de) 1978-07-06

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