JPS53101242A - Fibonacci code adder - Google Patents

Fibonacci code adder

Info

Publication number
JPS53101242A
JPS53101242A JP15500877A JP15500877A JPS53101242A JP S53101242 A JPS53101242 A JP S53101242A JP 15500877 A JP15500877 A JP 15500877A JP 15500877 A JP15500877 A JP 15500877A JP S53101242 A JPS53101242 A JP S53101242A
Authority
JP
Japan
Prior art keywords
code adder
fibonacci code
fibonacci
adder
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15500877A
Other languages
English (en)
Other versions
JPS573100B2 (ja
Inventor
Piyootorouitsuchi Sut Arekusei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Original Assignee
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova filed Critical Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Publication of JPS53101242A publication Critical patent/JPS53101242A/ja
Publication of JPS573100B2 publication Critical patent/JPS573100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
JP15500877A 1976-12-22 1977-12-22 Fibonacci code adder Granted JPS53101242A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762432391A SU732864A1 (ru) 1976-12-22 1976-12-22 Сумматор кодов фибоначчи

Publications (2)

Publication Number Publication Date
JPS53101242A true JPS53101242A (en) 1978-09-04
JPS573100B2 JPS573100B2 (ja) 1982-01-20

Family

ID=20687540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15500877A Granted JPS53101242A (en) 1976-12-22 1977-12-22 Fibonacci code adder

Country Status (9)

Country Link
US (1) US4159529A (ja)
JP (1) JPS53101242A (ja)
CA (1) CA1103807A (ja)
DD (1) DD136317A1 (ja)
DE (1) DE2756832A1 (ja)
FR (1) FR2375655A1 (ja)
GB (1) GB1565460A (ja)
PL (1) PL109971B1 (ja)
SU (1) SU732864A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU840891A1 (ru) * 1978-05-15 1981-06-23 Винницкийполитехнический Институт Параллельный сумматор кодов фибоначчи
DE69613181T2 (de) * 1995-02-03 2002-01-31 Koninklijke Philips Electronics N.V., Eindhoven Anordnung zum kodieren einer sequenz von (n-1)-bit informationswörtern in eine sequenz von n-bit kanalwörtern sowie dekodieranordnung zum dekodieren einer sequenz von n-bit kanalwörtern in eine sequenz von (n-1)-bit informationswörtern
US6934733B1 (en) * 2001-12-12 2005-08-23 Lsi Logic Corporation Optimization of adder based circuit architecture
CN112787658B (zh) * 2020-12-31 2022-12-13 卓尔智联(武汉)研究院有限公司 基于斐波那契进制的逻辑运算电路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1547633A (fr) * 1967-10-16 1968-11-29 Labo Cent Telecommunicat Circuit d'addition de nombres binaires provenant du codage non linéaire de signaux

Also Published As

Publication number Publication date
PL109971B1 (en) 1980-06-30
JPS573100B2 (ja) 1982-01-20
GB1565460A (en) 1980-04-23
FR2375655A1 (fr) 1978-07-21
CA1103807A (en) 1981-06-23
US4159529A (en) 1979-06-26
DE2756832A1 (de) 1978-07-06
PL203158A1 (pl) 1978-12-18
SU732864A1 (ru) 1980-05-05
DD136317A1 (de) 1979-06-27
FR2375655B1 (ja) 1980-08-22

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