CA1088676A - Enhancement-mode fets and depletion-mode fets with two layers of polycrystalline silicon - Google Patents

Enhancement-mode fets and depletion-mode fets with two layers of polycrystalline silicon

Info

Publication number
CA1088676A
CA1088676A CA281,849A CA281849A CA1088676A CA 1088676 A CA1088676 A CA 1088676A CA 281849 A CA281849 A CA 281849A CA 1088676 A CA1088676 A CA 1088676A
Authority
CA
Canada
Prior art keywords
mode
depletion
enhancement
regions
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA281,849A
Other languages
English (en)
French (fr)
Inventor
Vincent L. Rideout
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/702,247 external-priority patent/US4085498A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1088676A publication Critical patent/CA1088676A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
CA281,849A 1976-07-02 1977-06-30 Enhancement-mode fets and depletion-mode fets with two layers of polycrystalline silicon Expired CA1088676A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/702,247 US4085498A (en) 1976-02-09 1976-07-02 Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps
US702,247 1976-07-02

Publications (1)

Publication Number Publication Date
CA1088676A true CA1088676A (en) 1980-10-28

Family

ID=24820425

Family Applications (1)

Application Number Title Priority Date Filing Date
CA281,849A Expired CA1088676A (en) 1976-07-02 1977-06-30 Enhancement-mode fets and depletion-mode fets with two layers of polycrystalline silicon

Country Status (5)

Country Link
JP (1) JPS535978A (enrdf_load_stackoverflow)
CA (1) CA1088676A (enrdf_load_stackoverflow)
DE (1) DE2723254A1 (enrdf_load_stackoverflow)
GB (1) GB1522294A (enrdf_load_stackoverflow)
IT (1) IT1113770B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device
CN118398494B (zh) * 2024-06-28 2024-09-27 合肥欧益睿芯科技有限公司 E/D集成的GaAs HEMT器件及其制造方法、电路和电子设备

Also Published As

Publication number Publication date
GB1522294A (en) 1978-08-23
JPS535978A (en) 1978-01-19
DE2723254C2 (enrdf_load_stackoverflow) 1987-10-08
JPS5525515B2 (enrdf_load_stackoverflow) 1980-07-07
DE2723254A1 (de) 1978-01-12
IT1113770B (it) 1986-01-20

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Legal Events

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