GB1522294A - Semiconductor devices - Google Patents

Semiconductor devices

Info

Publication number
GB1522294A
GB1522294A GB25028/77A GB2502877A GB1522294A GB 1522294 A GB1522294 A GB 1522294A GB 25028/77 A GB25028/77 A GB 25028/77A GB 2502877 A GB2502877 A GB 2502877A GB 1522294 A GB1522294 A GB 1522294A
Authority
GB
United Kingdom
Prior art keywords
fet
depletion
polycrystalline silicon
electrode
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB25028/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/702,247 external-priority patent/US4085498A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1522294A publication Critical patent/GB1522294A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

1522294 Complementary field effect transistors INTERNATIONAL BUSINESS MACHINES CORP 15 June 1977 [2 July 1976] 25028/77 Heading H1K A method of fabricating an enhancementmode FET and a depletion-mode FET in a semiconductor substrate involves five lithographic masking steps which delineate in order (1) field isolation regions 3; (2) an enhancementmode FET gate electrode 13 from a first doped polycrystalline silicon layer; (3) a depletionmode FET gate electrode 22 from a second and subsequently formed polycrystalline silicon layer; (4) contact holes to FET source and drain regions and to the depletion-mode FET gate (Fig. 2D, not shown) and (5) a relatively high electrical conductivity inter-connecting pattern 34. The self-aligned enhancement mode FET gate electrode 13 is used as n-type ion-implantation mask during the formation of doped, lower electrode 15 of a storage capacitor and the channel region 14 of the depletion-mode FET. The polycrystalline silicon gate pattern 22 and an upper electrode pattern 23 of the storage capacitor are formed simultaneously by chemical etching using a photo-resist mask, and the electrode patterns are subsequently used as a mask during the formation of source and drain regions 24-27.
GB25028/77A 1976-07-02 1977-06-15 Semiconductor devices Expired GB1522294A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/702,247 US4085498A (en) 1976-02-09 1976-07-02 Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps

Publications (1)

Publication Number Publication Date
GB1522294A true GB1522294A (en) 1978-08-23

Family

ID=24820425

Family Applications (1)

Application Number Title Priority Date Filing Date
GB25028/77A Expired GB1522294A (en) 1976-07-02 1977-06-15 Semiconductor devices

Country Status (5)

Country Link
JP (1) JPS535978A (en)
CA (1) CA1088676A (en)
DE (1) DE2723254A1 (en)
GB (1) GB1522294A (en)
IT (1) IT1113770B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device

Also Published As

Publication number Publication date
JPS5525515B2 (en) 1980-07-07
DE2723254A1 (en) 1978-01-12
DE2723254C2 (en) 1987-10-08
IT1113770B (en) 1986-01-20
CA1088676A (en) 1980-10-28
JPS535978A (en) 1978-01-19

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee