JPS535978A - Method of forming enhancement fet and depletion fet - Google Patents

Method of forming enhancement fet and depletion fet

Info

Publication number
JPS535978A
JPS535978A JP7565077A JP7565077A JPS535978A JP S535978 A JPS535978 A JP S535978A JP 7565077 A JP7565077 A JP 7565077A JP 7565077 A JP7565077 A JP 7565077A JP S535978 A JPS535978 A JP S535978A
Authority
JP
Japan
Prior art keywords
fet
depletion
forming enhancement
forming
enhancement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7565077A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5525515B2 (enrdf_load_stackoverflow
Inventor
Eru Raidoauto Binsento
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/702,247 external-priority patent/US4085498A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS535978A publication Critical patent/JPS535978A/ja
Publication of JPS5525515B2 publication Critical patent/JPS5525515B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP7565077A 1976-07-02 1977-06-27 Method of forming enhancement fet and depletion fet Granted JPS535978A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/702,247 US4085498A (en) 1976-02-09 1976-07-02 Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps

Publications (2)

Publication Number Publication Date
JPS535978A true JPS535978A (en) 1978-01-19
JPS5525515B2 JPS5525515B2 (enrdf_load_stackoverflow) 1980-07-07

Family

ID=24820425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7565077A Granted JPS535978A (en) 1976-07-02 1977-06-27 Method of forming enhancement fet and depletion fet

Country Status (5)

Country Link
JP (1) JPS535978A (enrdf_load_stackoverflow)
CA (1) CA1088676A (enrdf_load_stackoverflow)
DE (1) DE2723254A1 (enrdf_load_stackoverflow)
GB (1) GB1522294A (enrdf_load_stackoverflow)
IT (1) IT1113770B (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5359384A (en) * 1976-09-13 1978-05-29 Texas Instruments Inc Nnchannel mos silicon gate ram cell
CN118398494A (zh) * 2024-06-28 2024-07-26 合肥欧益睿芯科技有限公司 E/D集成的GaAs HEMT器件及其制造方法、电路和电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5359384A (en) * 1976-09-13 1978-05-29 Texas Instruments Inc Nnchannel mos silicon gate ram cell
JPS6150361A (ja) * 1976-09-13 1986-03-12 テキサス インスツルメンツ インコ−ポレイテツド メモリセル
CN118398494A (zh) * 2024-06-28 2024-07-26 合肥欧益睿芯科技有限公司 E/D集成的GaAs HEMT器件及其制造方法、电路和电子设备

Also Published As

Publication number Publication date
CA1088676A (en) 1980-10-28
GB1522294A (en) 1978-08-23
DE2723254C2 (enrdf_load_stackoverflow) 1987-10-08
JPS5525515B2 (enrdf_load_stackoverflow) 1980-07-07
DE2723254A1 (de) 1978-01-12
IT1113770B (it) 1986-01-20

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