CA1078078A - Schottky barrier semiconductor device and method of making same - Google Patents

Schottky barrier semiconductor device and method of making same

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Publication number
CA1078078A
CA1078078A CA273,141A CA273141A CA1078078A CA 1078078 A CA1078078 A CA 1078078A CA 273141 A CA273141 A CA 273141A CA 1078078 A CA1078078 A CA 1078078A
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Prior art keywords
layer
substrate
glow discharge
silane
amorphous silicon
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CA273,141A
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French (fr)
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David E. Carlson
Christopher R. Wronski
Alfred R. Triano (Jr.)
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RCA Corp
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RCA Corp
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Priority claimed from US05/710,186 external-priority patent/US4142195A/en
Application filed by RCA Corp filed Critical RCA Corp
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/503Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using dc or ac discharges
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
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    • H01L21/02474Sulfides
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104Forming layers
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/07Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the Schottky type
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

A SCHOTTKY BARRIER SEMICONDUCTOR DEVICE AND
METHOD OF MAKING SAME
ABSTRACT

A first layer of semiconductor device is of doped amorphous silicon prepared by a glow discharge in a mixture of silane and a doping gas. The first layer is on a substrate having good electrical properties. On the first layer and spaced from the substrate is a second layer of amorphous silicon prepared by a glow discharge in silane. On the second layer opposite the first layer is a metallic film forming a surface barrier junction there-between, i.e. a Schottky barrier. The first layer is doped so as to make an ohmic contact with the substrate.
Preferably the doping concentration of the first layer is graded so the dopant concentration is maximum at the interface of the first layer and the substrate. In a second embodiment of the Schottky barrier semiconductor device an intermediate layer is between and contiguous to both the first layer and the substrate. The intermediate layer facilitates in making ohmic contact between the amorphous silicon and the substrate. Annealing and heat treating steps are performed in the fabrication of the Schottky barrier device to increase device efficiency.

Description

10>78378 The present invention relates to semiconductor devices and more particularly to photovoltaic devices and current rectifying devices utilizing amorphous silicon prepared by a glow discharge in silane.
Photovoltaic devices such as solar cells and photodetectors are capahle of converting light, i.e. infrared through the ultraviolet range, into usable electrical energy.
A problem encountered in the field of solar cells is that the cost of producing electrical energy from solar cells is often not competitive with other means of electrical energy generation. One of the largest expenses involved in solar cell manufacture is the cost of the semiconductor material utilized in the solar cell. Naturally, the more semiconductor material needed the higher the cost of a solar cell. The lowering of the amount of semiconductor material needed for photodetector devices would also lo~er their cost.
If this same semiconductor ~aterial demonstrates current rectification properties in the dark, it could also be utilized in semiconductor devices such as diodes.
It has recently been discovered that the bodies of photovoltaic and current rectifier devices can be made very thin if they are of amorphous silicon prepared by a glow discharge in silane. However, a problem encountered in some of these devices is the makinq of an ohmic contact to amorphous silicon prepared by a glow discharge in silane.

Thus, it would be most desirable in the semiconductor field to have a device that utilizes amorphous silicon with its 1 aeeompanying benefits and also allows ohmic contact to he made to the amorphous silicon.

A Sehottky barrier semiconductor device ineludes an annealed body of amorphous doped silicon fabricated by a glow discharge in silane. A metallic film is on a surface of the body providing a surface barrier junction at the interfaee of the metallic film and the body.

FIG. l is a eross-seetional view of the first embodiment of the Sehottky barrier semieonduetor deviee of the present invention.
FIG. 2 is a graph eomparing the absorPtion co-effieient of single crystal silieon to glow diseharge amorphous silieon in the visible liqht range.
FIG. 3 is a sehematie view of a first apparatus for earrying out the fabrication of amorphous silieon by a glow diseharge in silane.
FIG. 4 is a sehematie view of a second apparatus for earrying out the fabrication of the amorphous silieon by a glow diseharge in silane.
FIG. 5 is a cross-seetional view of the seeond embodiment of the Sehottky barrier semiconductor device of the present invention.

Referring to FIG. l, a first embodiment of the Schottky barrier semieonduetor deviee of the present invention is designated as lO. The Schottky barrier semieonduetor device lO is subsequently described as a solar cell for the purposes of explaining the present invention. The semi--- 3 ~

10780'78 I conductor device 10 includes a substrate 12 of a rnaterial preferably having good electrical conductivity properties.
Materials having this capability are typically aluminum, chromium, stainless steel, niobium, tantalum, iron and indium tin oxide on glass, where the indium tin oxide is the conductive material.
On a surface of the substrate 12 is a body 13 of amorphous silicon fabricated by a glow discharge in silane, SiH4. The method of deposition well known to those in the art as glow discharge involves the discharge of electricity through gas at relatively low pressure, i.e.
ahout 5 torrs or less, in a partially evacuated chaT~ber.
A glow discharge is characterized by several regions of diffuse, luminous glow, i.e. the positive column which is near the anode and the negative glow which is hetween the anode and cathode, and a voltage drop in the vicinity of the cathode that is much higher in potential than the ionization potential of the gas, i.e. the Crookes dark space region.
An amorphous ~aterial is one which has no long range order in the periodicity of the matrix. Amorphous silicon fabricated by a glow discharge in silane, SiH4, possesses a short range order of no more than 20A. The lack of long range order of an amorphous silicon material fabricated hy a glow discharge in silane can be detected by X-ray or electron diffraction.

The body 13 includes a first layer 14 of amorphous silicon fabricated by a glow discharae in a mixture of silane and a doping gas. The first layer 14 is capable of having an ohT~ic contact with the substrate 12, 1078~8 RCA 70335A

1 and having a first interface 15 therehetween. A second layer 16 of amorphous silicon of the body 13 is on the first layer 14 opposite the suhstrate 12. The second layer 16 is fabricated by a glow discharge in silane, SiH4, and typically by a glow discharge in substantially pure silane.
Since the glow discharge may be in substantially pure silane, it would be anticipated that the second layer 16 is undoped, but it has been discovered that the second layer 16 even if fabricated in pure silane is lightly N- doped, i.e. for deposition on a deposition surface heated to a temperature greater than 100C. The first and second layers 14 and 16 are of the same conductivity type.
Preferably the dopant concentration of first layer 14 is graded such that the concentration of the dopant is a maximum at the interface 15 and decreases to an insignificant concentration at the interface of first layer 14 and second layer 16. Although it is preferred th~t the first layer have a graded doping concentration, for reasons sub-sequently explained, it is also anticipated hy the present invention that the dopant concentration be uniform throughout the first layer 14.
The amorphous silicon of the first and second layers 14 and 16 is formed by a glow discharge in silane plus an appropriate doping gas for layer 14, and can he distinguished from other amorphous silicon in that it has the kinetic characteristics of an average density of localized states in the energy gap on the order of 10~7/cm3 or less. The average density of localized states is determined by plotting the ratio of one over the capacitance squared (l/C ) as a function of voltage for the amorPhous 1 silicon semiconductor device. From the shape of this plot the average density of localized states can be determined by those skilled in the art. For amorphous silicon fabrication by a glow discharge in silane the drift mobility for electrons is 10 3cm2/V-sec. or greater. The drift mobility for electrons is measured by the well known technique of impinging light pulses or electron beam pulses on the biased semiconductor device and the subsequent flow of electrons generated by the pulses is followed by a sampling system. Furthermore, it has been estimated from photoconductivity measurements that the electron carrier lifetime of amorphous silicon fabricated by a glow discharge in silane is on the order of 10 5 seconds.
Although it is ant~ci~ated that amorphous silicon fabricated by a glow discharge in silane with an electron lifetime on the order of 10 7 seconds or greater will also possess good elec-trical characteristics.
The first layer 14 is typically in the range of 100 A to about 0.5 microns in thickness and the second layer 16 is about one-half to one micron in thickness.
On a surface of the second layer 16 opposite the first layer 14 is a metallic film 18, with an interface 20 therebetween. The metallic film 18 is at least semi-trans-parent to solar radiation when the device is to be used as a solar cell, and is of a metallic material with good electrical conductivity and of a high work function, i.e. greater than 4.5eV, assuming the second layer 16 is of an N-type conducti-vity. Metallic materials having good electrical conductivity and a high work function are, for example, gold, silver, platinum, palladium, rhodium, iridium or chromium. The ~ metallic film 18 may be a single layer of a metal or it may ~078078 1 be multi-layered. If the metallic film 18 is multi-layered a first layer could be of platlnum on the second layer 16 and a second layer on the first platinum layer could be gold or silver for good electrical conductivity. As stated previously, when the device is a solar cell, the metallic film 18 is at least semi-transparent to solar radiation, and since it is a metal it should be on the order of about 100 A to assure semi-transparency.
Typically, the first layer 14 is of N type conducti-vity, although it is anticipated that the Schottky barrier de~ice of the present invention can also have a first layer 14 of P type conductivity. If the first layer 14 is of P type conductivity, the second layer 16 would be doped so that it is slightly P type and the metallic film 18 would be of a low work function metal, less than about 4.3eV, e.g. aluminum.
On a portion of the surface of the metallic film 18 opposite the interface 20 is an electrode 22. Typically, the electrode 22 is in the shape of a grid, although it can be of other shapes well known to those in the art, e.g. finger or comb shaped, and it is of a metal having good electrical conductivity.
The electrode 22 for purposes of disclosing the present invention has two sets of grid lines, with the grid lines of each set substantially parallel to each other and intersecting the grid lines of the other set. The electrode 22 occupies only a small area on the surface of the metallic film 18, i.e. about 5 to 10~ of the film 18 surface area, since solar radiation impinging the electrode 22 may be reflected away from the device 10. The function of the electrode 22 is for the uniform collection of current from 1078~78 1 the metallic film 18. The electrode 22 facilitates in keeping the series resistance of the device 10 low when in operation as part of a circuit. However, it is anticipated that only a single set of grids may be necessary for uniform current collection in small surface area devices thereby being in the form of what is known in the art as a fingered or comb shaped electrode.

An antireflection layer 24 is on the electrode 22 and on the surface of the metallic film 18 op~osite the interface 20 not occupied by the electrode 22. The anti-reflection layer 24 has an incident surface 26 on which solar radiation 28 is capable of impinging. As is well known in the art, there is an increase in the solar radiation 28 traversing the metallic film 18 and entering the device 10 by having the antireflection layer 24 of a thickness on the order of ~/n, wherein ~is the wavelength of the radiation impinging the incident surface 26, and n is the index of refraction of the antireflection layer 24.
The index of refraction, n, of the antireflection layer 24 should be of an appropriate value to increase the amount of solar radiation 28 impinging the metallic film 18.
For example, if the metallic film 18 is platinum, lOOA
in thickness, a suitable antireflection layer 24 would be of zirconium oxide, ZrO2, about 500A in thickness with n = 2.1. In essence, the antireflection layer 24 reduces the amount of light that would be reflected from the device 10. Usually, the antireflection layer 24 will be of a dielectric material such as zinc sulfide, zirconium oxide, 0 or silicon nitride, but can be a transparent semiconductor 1 such as tin oxide doped with antimony, or indiu~ oxide doped with tin.
In the field of se~iconductor devices ~t is well known that a surface barrier junction, generally known as a Schottky barrier, is formed as a result of the contacting of certain metals to certain semiconductor materials. In the Schottky barrier semiconductor device 10 of the present invention, the barrier junction is formed at the interface 20 by contacting the ~etallic film 18 to the second layer 16. A Schottky barrier generates a space charge or electric field in the semi-conductor material of device 10 from the interface 20 which penetrates into the second layer 16 and is referred to as the depletion region. Also, as a result of the graded doping concentration of the first layer 14 an electric field is created in the first layer 14.
Therefore, with the .Schottky barrier at interface 20 and the graded dopant concentration of the first layer 14 an electric field extends essentially through both the first and second layers 14 and 16. It is preferable for at least photovoltaic devices of the present invention that the electric field extend through the first and second layers 14 and 16. With the electric field extending through the first and second layers 14 and 16, carriers created anywhere within these layers, as a result of the absorption of solar radiation 28, are swept by the electric field to either the suhstrate 12 or the ~etallic region 18.
The substrate 12 functions as one of the electro~es of devi~e 10. If the electric field does not extend into a portion of the first or second layers 14 and 16 of g I device 10, any carriers generated in this quasi-neutral portion would not he swept to an electrode by means of a field and must rely on diffusion to the depleted region in order to be collected. Also, any quasi-neutral region may contribute to the series resistance when drawing current from the device, and this series resistance would lower device efficiency.
While the graded doping concentration of first layer 14 is advantageous in lenqthening the electric field region of the device 10, in addition an ohmic contact can more readily be formed between the first layer 14 and substrate 12 because the doping concentration is maximum at the first interface 15, i.e. on an order of 5 atomic percent. The forming of an ohmic contact at interface 15 is advantageous in assuring a low series resistance for the semiconductor device 10. Even if the first layer 14 has a uniform dopant concentration throughout, an ohmic contact can be formed at interface 15 as long as the uniform dopant concentration is on the order of 5 atomic percent.
The amorphous silicon of the first layer 14 fabricated by a glow discharge in silane plus a doping gas, and the amorphous silicon of the second layer 1 fabricated by a glow discharge in silane possesses characteristics ideally suited for photovoltaic devices.

Electron lifetime in amorphous silicon fabricated by a glow discharge in silane is estimated to be on the order of about 10 seconds, while electron lifetime in amorPhous silicon formed by sputtering or evaporation is in the order of 10-11 seconds-~CA 70335A
10780'78 I Also measurements of the spectral res~onse of the device of the present invention indicates a high collection efficiency throuqh the visible portion of the spectrum, e.g. the average collection efficiency in the spectral range of 4,000A to 7,000A is on the order of 5n%.
The optical absorPtion of the glow discharge amorphous silicon is superior to that of single crystalline silicon over the visible li~ht range, i.e. 4, OOOA to 7,~00~.
Referring to FIG. 2, it is shown that the amorphous silicon has a larger absorption coefficient over the visiblerange than single crystalline silicon. This means that a body of glow discharge a~orphous silicon can be a factor of 10 thinner than single crystal silicon and provide comparable light absorption in the visi~le range.
Furthermore, the average density of localized states in the energy gap of glow discharge amorPhous silicon is on the order of 1017/cm3 or less. The average density of localized states of glow discharge amorphous silicon decreases with increasing deposition temperature and increasing nurity of the silane in the fabrication of the amorphous silicon. This average density of localize~
states of the glow discharge amorphous silicon is much lower than that of amorphous silicon fabricated by other means, i.e., for sputtered or evaporated amorphous silicon the average density of localized states is 1019/c~3 or greater. ~ignificant about the av~rage density of localized states in the energy gap is that it is inversely prcportional to the square of the width of the depletion region. Since glow discharqe amorphous silicon's density 3 of states is relatively low, a depletion width on the order 1 of one micron can he obtained. Also, significant about the average density of localized states near ~id-gaP is the fact that carrier lifeti~e is inversely proportional to the average density of states. This Point reaffirms that the carrier lifetime o~ glow discharge amorphous silicon is larger than that of amorphous silicon fabricated by the other processes mentioned.
Referring to FIG. 3, a glow discharge apparatus suitable for carrying out the fabrication of the semi-conductor device 10 of the present invention is qenerallydesignated as 30. The qlow discharge apparatus 3~ in-cludes a chamber 32 defined by a vacuum bell 34, tyPically of a glass material. In the vacuum chamber 32 is an electrode 36, and a heating plate 38 sp~ced from and opposite the electrode 36. The electrode 36 is of a metallic material having good electrical conductivity such as platinum and is in the form of a screen or coil. The heating plate 38 is a ceramic frame with enclosed heating coils which are energized fro~ a current source 40, external to the vacuum chamber 32.
A first outlet 44 into the vacuum chamber 32 is connected to a diffusion pump, a second outlet 46 is connected to a mechanical pump~ and a third outlet 48 is connected to a gas bleed in system which is the source of the various gases utilized in the glo~ discharge process.

While the second outlet 46 is described as being connected to a diffusion pump, it is anticipated that a diffusion pump may not be necessary since the mechanical PumP

connected to the first outlet 44 may evacuate the system to a sufficient pressure.

RCA 70335~

1~78078 1 In the fabrication of the semiconductor device 10, the substrate 12, e.g. ~3oa stainless steel, is placed on the heating plate 38 and is connected to one ter~inal of a power source 42 and the electrode 36 connected to an opposite terminal of power source 42. A voltage potential therefore exists between the electrode 36 and substrate 12.
The power source 42 can be either DC or it can he i.e. in the low frequency ran~e for example 60 Hertz, or it can be R. F., i.e. in the high frequency range, for exa~ple on the order of megahertz. Typically, when the power source 42 is DC the electrode 36 is connected to the positive terminal of the power source 42, and the substrate 12 is connected to the negative terminal of the power source 42. Thus, the electrode 36 functions as an anode and the substrate 12 functions as a cathode when the power source 42 is energized. This is referred to as a cathodic DC operation. However, in DC operation the substrate 12 and electrode 36 can be of the oPposite polarities described, i.e. the substrate 12 is the anode and the electrode 36 is the cathode, which is referred to an anodic DC operation. It has been discovered that the deposition rates are somewhat higher in the cathodic mode than in the anodic mode. Furthermore, R. F. glow discharge operation can be accomplished in electrode less glow discharge apparatus of a type well kno~wn ~tothose in the art, e.g. capactive R. F. glow discharge system and inductive R. F. glow discharge system. However, more uniform deposition over a large area, i.e. greater than lOcm2, is attained in DC

or AC glow discharge than in electrode less, R. F. glow 0 discharge. Next, the vacuum chamber 32 is typically RCA 70335~ ' 10780~78 1 evacuated to a pressure of about 10 3 to 10 6 torrs, and the substrate 12 is heated to a temPerature in the ranqe of 150 to 450C. by energizing the heating coils of the heating plate 38.
Then, an atmosphere of ahout 98.5% silane, SiH~, and ahout 1.5~ N type dopant gas, is bled into the vacuum chamber 32 to a pressure of 0.1 to 5.0 torrs and as a result the substrate temperature is raised to a value in the range of 200C. to 500C. Typical N type dopant gases which may be utilized in glow discharge processes arephosphine, PH3, and arsine, AsH3. Also, materials such as antimony, Sb, hismuth, Bi, sodiu~ hydride, NaH, and cesium nitride, CsN , can be used by placing them in an evaporation hoat and heating them in the atmosphere of the vacuum chamher 32 until the desired amount of the dopant gas or vapor is release~ into the silane atmosphere.
To initiate the qlow discharge between the electrode 36 and the substrate 12, the power source 42 is energized, thereby commencing the deposition of th~ doped amorphous silicon layer 14. The cathodic mode of operation is assumed. For deposition of the first layer 14 the current density should be in the ranqe of 0.1 to 3.0 ma/cm2 at the surface of the substrate 12. The deposition rate of the amorphous silicon increases with the vapor pressure of the silane and the current density. For a pressure of 2 torrs and current density of 1 ma/cm2 to a cathodic substrate 12 at 350C., the deposition of approximately 200A of doped anorphous silicon occurs in a few seconds. To,grade the dopant concentration of the first layer 14, additional silane is bled into the vacuum ; - 14 -1C~781~78 I chamber 32 during the glow discharge deposition.
Once the glow discharge is initiated for the DC
cathodic mode, electrons from the suhstrate 12 are emitted from the substrate and strike silane molecules, SiH4, both ionizing and disassociating the molecules. The positive silicon ions and positive silicon hydride ions such as SiH , are attractea to the substrate 12, which is the cathode and silicon containing some hydrogen is there~y deposited on the suhstrate 12. It is believed that the presence of hydrogen in the amorphous silicon is beneficial to its electronic properties.
The atmosphere in the vacuum chamber 32 is then pumped out by the mechanical pump 46.
With the vacuum chamber 32 at a pressure of about 10 6 torrs, substantially pure silane is bled into the vacuum chamber 32 at a pressure in the range of ~.1 to 5 torrs. Again a glow discharge is initiated for 1 to 5 minutes with a current density of from 0.3 ma/cm to 3.0 ma/cm at the first layer 14 for the deposition of the second layer 16 of amorphous silicon. It has heen found that the second layer 16 of amorphous silicon fabricated by a glow discharge in substantially pure silane is of a slightly N-type conductivity, when deposited on ~ first layer 14 which is at a temperature above 100C.
The temperature of the substrate 12 in the glow discharge process may influence the composition and structure of the material deposited thereon due to the effects of auto doping, eutectic formation and induced crystallization, e.g. deposition on a single crystalline silicon substrate at temperatures above about 500C. results in the deposition RC~ 70335A

~078~78 I of a polycrystalline silicon, and deposition on a gold substrate at a temperature ahove 186C. results in induced crystallization of the deposited silicon.
After deposition of the first and second layers 14 and 16 the body 13 can be annealed hy subjecting the body 13 to a temperature in the range of 200C. to 450C.
for a few minutes to several hours. It is anticipated that the annealing step will require several hours only for the lower annealing temperatures. Typically, annealing can be accomplished by leaving the body 13 in the glowdischarge apparatus 30 after the glow discharge is terminated, or by placing the wafer in an annealing furnace of the type well known to those in the art. The annealing may take place in either an evacuated atmosphere or in a forming IS gas atmosphere, e.g. 90% nitrogen and 10% hydrogen by volume or at~ospheres of pure nitrogen or pure hydrogen.
This processing step anneals out lattice defects in the amorphous silicon body 13 and has been found to improve device efficiency.
Next, the body 13 is placed in a state of the art evaporation system and the metallic film 18 is evaporated onto the second layer 16. Likewise, the electrode 22 and antireflection layer 24 are deposited on the metallic film 18 by state of the art evaporation and masking techniques.
The entire processing may be accomplished in a single system accom~odating both glow discharge and evaporation.
It has also been discovered that when the semi-conductor device 10 having a metallic film 18 of a material selecced from the group consisting of chromium, iridium, rhodium, platinum, or palladiu~ is subjected to a heat RC~ 70335A
lC78G78 I treatment during fabrication, the collection efficiency of the device increases. Typically, the heat treatment step can occur after the antireflection layer 24 is dePosited, or it may occur both prior to deposition of the elec~rode 22 and after deposition of the antireflection layer 24.
Specifically, the heat treatment involves placing the semi-conductor device 10 in a heat treating chamher of a type well known to those in the art and subjecting the device 10 to a temperature in the range of 150C. to 250C. for about 5 to 30 minutes. The heat treating chamber may be evacuated or have a forming gas atmosphere, e.g. 90~ nitrogen and 10% hydrogen by volume or atmospheres of pure nitrogen or pure hydrogen. This heat treating step has been found to increase device efficiency, by causing an increase in Schottky barrier height, improvement in collection efficiency and reduction in effective series resistance of the device.
Fabrication of the semiconductor device 10 is comPleted by the connecting of wire electrodes (not shown) to the suh-strate 12 and electrode 22 for connection to external circuitry.
In operation of the se~iconductor device 10 the substrate 12 ~ay reflect unabsorbed solar radiation back into the first and second layer 14 and 16, thereby improv-ing the possibility for solar radiation absorption.
Referring to FIG. 4, a second glow discharqe apparatus for the fabrication of the se~iconductor device 10 is designated as 130. The apparatus 130 is similar to the apparatus 30. Specifically, vacuum chamber 132, vacuum bell 134, electrode 136, heatin~ plate 138, current source 140, power source 142, first outlet 144, second out-RC~ 70335A

1 let 146 and third outlet 148 of apparatus 130 are the same as vacuum cha~ber 32, vacuum bell 34, electrode 36, heating plate 38, current source 40, power source 42, first outlet 44, second outlet 46 and third outlet 48 of aPparatus 30 respectively. Apparatus 130 unlike apparatus 30 has an electrode 149, which is in the form of a screen. The screen electrode 149 is of an electrically conductive material such as a metal like stainless steel, and has openings therein which are smaller in size than the cathode dark space region of the glow discharge. The screen electrode 149 is between the electrode 136 and heating plate 138 and is spaced over the substrate 12 a distance which is on the order of the cathode dark space region of the glow discharge.
The operation of apparatus 130 differs from that of apparatus 30 in that the suhstrate 12 is not electrically connected to the power source 142, instead the screen electrode 149 is electrically connected to the power source 142. Thus, the screen electrode 149 is connected to one terminal of power source 142 and the electrode 136 is connected to the opposite terminal. If a DC cathodic mode of operation is assumed, when the power source 142 is energized and a glow discharge initiated, the positive ions in the glow discharge are drawn to the screen electrode 149. However, most of the positive ions will pass through the openings in the screen electrode 149.
The apparatus 130 having the screen electrode 149 can be used when the substrate lZ is an insulator to which no electrical contact can be made. However, the apparatus 130 can also be utilized in the fabrication of amorphous silicon devices in which the substrate 12 is not 107~8 RCA 70335A

1 an insulator.
The apparatus 130, like the apparatus 30, can be operated in the DC cathodic or anodic modes.
Referring to FIG. 5, a second embodiment of the Schottky barrier semiconductor device of the present invention is designated as 110. The semiconductor device 110 includes an electrically conductive substrate 112. On a surface of the substrate 112 is an intermediate layer 111 with a body 113 on the intermediate layer 111. The hody 113 includes a first layer 114 on the intermediate layer 111 opposite the substrate 112, and a second layer 116 on the first layer 114 opposite the suhstrate 112. A semi~
transparent metallic film 118 is on the second layer 116 opposite the substrate 112 forming a surface harrier junction therebetween. On a portion of the metallic film 118 is an electrode 122 with an antireflection layer 124 on the remaining portion of the metallic film 118 and on the electrode 122. The substrate 112, first layer 114, second layer 116, metallic film 118, electrode 122 and antireflection layer 124 of device 110 are the same as the substrate 12, first layer 14, second layer 16, metallic film 18, electrode 22 and antireflection layer 24, of the se~iconductor device 10, respectively. The only difference between semiconductor device 10 and semiconductor device 110 is that device 110 has an intermediate layer 111 which device 10 does not.
The intermediate layer 111 is of a material that will make ohmic contact to both the substrate 112 and first layer 114. Typically, the intermediate layer 111 will be of doped amorphous germanium or of a doped amorphous germanium-silicon alloy. For either material the layer 111 10780~78 1 is usually of N type conductivity if the second layer 16 is slightly N type. It has been found that amorPhous germanium is a good material for forming an ohmic contact between doped amorphous silicon and metallic substrate 112.
Particularly when the substrate 112 is of alu~inum the electrical conductivity between the first and second layers 114 and 116 of device 110 and substrate 112 is better than the electrical conductivity between the first and second layers 14 and 16 of device 10 and substrate 12.

The operation of the Schottky barrier semiconductor device 110 is the same as that described for the semi-conductor device 10. The fabrication of the semiconductor device 110 is similar to that of device 10 except that the intermediate layer 111 is deposited by a glow discharge onto the substrate 112 prior to the deposition of the first layer 114 by a glow discharge. Referring to FIG. 3, the fabrication of the intermediate layer 111 is accomplished by placing the substrate 112 on the heating plate 38, heat-ing the substrate to a temperature in the range of 150C.
to 450C. and evacuating the chamber 32 to a pressure of a~out 0.5 to 1.0 x 10 6 torrs. Next, gases determined by the desired compositions of the intermediate layer 111 are bled into chamber 32 to a pressure in the range of 0.1 to 5.0 torrs. If the intermediate layer 111 is to be of doped germanium the atmosphere comprises about g9~ germane, GeH4, and about 1% of a doping gas such as the N type doping gas phosphine, PH3. If the intermediate layer 111 is to be of doped germanium-silicon alloy the atmosphere may include about 60% germane, GeH430 and about 0.5% of a doping gas such as the N type doping ~ 20 -gas phosphine PH3. The glow discharge is then initiatedand continues for about 2 seconds for the deposition of the intermediate layer lll about 200A in thickness. The atmosphere in the vacuum chamber 32 is then pumPed out by the mechanical pump 46. The remainder of the semi-conductor device llO fabrication is the same as that previously described for the semiconductor device lO.
Although the semiconductor devices lO and llO
of the present invention have been described as solar cells, it is anticipated that semiconductor devices lO and llO
can be utilized as a high frequency photodetector, i.e.
a device which responds to radiant enerqy. It has been discovered that these photodetectors having a first layer of doped amorphous silicon contiguous to a second layer of amorphous silicon prepared by a glow discharqe in silane have a high frequency response on the order of lO
MHz or more. In utilizing the semiconductor devices lO
and llO as a photodetector it is well known by those in the semiconductor art that the amount of radiant energy entering the device may not be as critical as if the devices lO and ilO were used as a solar cell. Therefore, modifications obvious to those in the art can be made to the devices lO and llO if it is to function as a photo-detector, e.g. removal of antireflection layer and the replacement of the grid electrode with a contact pad.
The ut~lization of glow discharge amorphous silicon in the photovoltaic and photodetector devices of the present invention provides devices with a thinner body than devices of the same basic structure but of single crystalline silicon. Also devices utilizing glow I discharge amorphous silicon are capable of solar radiation absorption comparahle to that of single crystal silicon photovoltaic and photodetector devices having bodies of a factor of 10 times thicker. Thus, the specific advantage of the present invention as a photovoltaic or photodetector device is the cost reduction realized by the utilization of a thinner active region. Moreover, the present invention as a photovoltaic device ~lso provides a cost reduction in generation of electrical power from solar radiation because there is less energy expended in making devices of the present invention since fahrication is at temperatures lower than sin~le crystal device fahrication; and larqer area solar cells can he fahricated as compared to single crystalline solar cell fabrications.
It has also been discovered that the semiconductor devices 10 and 110 are capable of current rectification in the dark. As an example the .Schottky barrier semi-conductor device 10, with a suhstrate 12 of ~304 stainless steel, a uniform phosphorous doped first layer 14, a metallic film 18 of palladium, l,OOOA to 2,000A in thickness so as to function as an electrical contact, and without the grid electrode 22 and antireflection layer 24, demonstrates a current rectification ratio of 104 at - 0.4 volts. While the devices 10 and 110 were described as solar cells but can function as current rectifiers, it would be obvious to those skilled in the semiconductor art that their utility as rectifiers would be more desirable with some minor modifications, such as the removal of the antireflection layers.
In the semiconductor device of the present I invention, the first layer is of do~ed a~or~hous silicon and the second layer is of a~orphous silicon, and the device can function as either a solar cell, photodetector or current rectifier.

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A Schottky barrier semiconductor device comprising:
a substrate having an electrically conductive surface, an annealed thin body of amorphous doped silicon fabricated by a glow discharge in silane, SiH4, on said surface; and a metallic film on a surface of said body providing a surface barrier junction at the interface between said metallic film and said body.
2. A device according to claim 1 in which said metallic film is at least semi-transparent to solar radiation.
3. A Schottky barrier semiconductor device according to claim 1 in which said body has a first layer of doped amorphous silicon on said substrate fabricated by a glow discharge in a mixture of silane and a doping gas, and a second layer of amorphous silicon fabricated by a glow discharge in silane on a surface of said first layer.
4. A Schottky barrier semiconductor device in accordance with claim 3 wherein said first layer is of N type conductivity.
5. A Schottky barrier semiconductor device in accordance with claim 4 wherein the dopant concentration of said first layer is graded such that it is a maximum at the interface between said first layer and said substrate and decreases in the direction of the interface between said first and second layers.
6. A device in accordance with claim 1 wherein said substrate is of aluminum.
7. A method of fabricating a Schottky barrier semiconductor device, comprising forming on a substrate having an electrically conductive surface, a thin body of amorphous doped silicon by a glow discharge in silane annealing said body at a temperature in the range of 200° C to 450° C for a few minutes to several hours, and depositing a film of metal on a surface of said body to form a surface barrier junction thereon.
8. A method according to claim 7 in which said body is made by forming on said substrate a first layer of doped amorphous silicon by a glow discharge in a mixture of silane and a doping gas; and forming a second layer of amorphous silicon by a glow discharge in silane on said first layer.
CA273,141A 1976-03-22 1977-03-03 Schottky barrier semiconductor device and method of making same Expired CA1078078A (en)

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CA1123525A (en) * 1977-10-12 1982-05-11 Stanford R. Ovshinsky High temperature amorphous semiconductor member and method of making same
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US4226898A (en) * 1978-03-16 1980-10-07 Energy Conversion Devices, Inc. Amorphous semiconductors equivalent to crystalline semiconductors produced by a glow discharge process
US4163677A (en) * 1978-04-28 1979-08-07 Rca Corporation Schottky barrier amorphous silicon solar cell with thin doped region adjacent metal Schottky barrier
JPS54145537A (en) * 1978-05-04 1979-11-13 Canon Inc Preparation of electrophotographic image forming material
DE2836911C2 (en) * 1978-08-23 1986-11-06 Siemens AG, 1000 Berlin und 8000 München Passivation layer for semiconductor components
DE2904171A1 (en) * 1979-02-05 1980-08-14 Siemens Ag METHOD FOR PRODUCING SEMICONDUCTOR BODIES MADE OF AMORPHOUS SILICON BY GLIMMER DISCHARGE
US4200473A (en) * 1979-03-12 1980-04-29 Rca Corporation Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer
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US4226643A (en) * 1979-07-16 1980-10-07 Rca Corporation Method of enhancing the electronic properties of an undoped and/or N-type hydrogenated amorphous silicon film
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JPS604274A (en) * 1983-06-22 1985-01-10 Toshiba Corp Photoelectric conversion member
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HK72084A (en) 1984-09-28
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FR2345810B1 (en) 1982-04-09
JPS52122471A (en) 1977-10-14
JPS616556B2 (en) 1986-02-27

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