CA1069221A - Anodic etching method for the detection of electrically active defects in silicon - Google Patents
Anodic etching method for the detection of electrically active defects in siliconInfo
- Publication number
- CA1069221A CA1069221A CA272,839A CA272839A CA1069221A CA 1069221 A CA1069221 A CA 1069221A CA 272839 A CA272839 A CA 272839A CA 1069221 A CA1069221 A CA 1069221A
- Authority
- CA
- Canada
- Prior art keywords
- silicon
- wafer
- defects
- electrically active
- method defined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2637—Circuits therefor for testing other individual devices
Abstract
ANODIC ETCHING METHOD FOR THE DETECTION OF
ELECTRICALLY ACTIVE DEFECTS IN SILICON
Abstract of the Disclosure Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is main-tained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semi-conductor devices to be formed later in the silicon structure.
ELECTRICALLY ACTIVE DEFECTS IN SILICON
Abstract of the Disclosure Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is main-tained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semi-conductor devices to be formed later in the silicon structure.
Description
18Back~round of the Invention 19Yield is a measure.of the success of a se~iconductor device processing sequence in producing quality ~inished 21 chips or wafers which are acceptable for their intended uses.
22 It is known that yield is adversely effected by the occurrences 23 of certain de~ects which can be introduced at various stages 24 of the device processing sl~quence. Clearly, it is advantageous to detect such occurrences at the earliest possible time so 26 that costly but futile additional processing steps normally z7 required to complete the devices are not undertaken. More ~ .
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1 particularly, it has been found that the defect count
22 It is known that yield is adversely effected by the occurrences 23 of certain de~ects which can be introduced at various stages 24 of the device processing sl~quence. Clearly, it is advantageous to detect such occurrences at the earliest possible time so 26 that costly but futile additional processing steps normally z7 required to complete the devices are not undertaken. More ~ .
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1 particularly, it has been found that the defect count
2 is a reliable predictor of yielcl of devices which are later
3 formed in the semiconductor material provided that the count
4 is limited to those defects which are electrically active, i.e., current carrying defects or leakage paths which can 6 result in shorted junctions or emitter-to-collector shorts, 7 for example. Defects which are not electrically active are 8 inconsequential to the performance of later fo~med devices 9 and, therefore, are not to be included in the defect count.
Summar~ of the Invention 11 Electrically active defects a`re detected in N type 12 silicon substrates and epitaxial layers by the anodic 13 etching of the semiconductor material exposed to a hydro-14 fluoric acid solution. In order to enhance the visual 15 discrimination between electrically~active defects and non- ;
16 electrically active defects (which do not affect device yield), 17 it is preferable that the concentration of the HF solution 18 employed be less than about 15~ and that the potential 19 difference between the solution and the semiconductor material be set so that the width of the resulting depletion layer 21 below the surface of the semiconductor material in contact 22 with the solution is commensurate with the depth of the 23 active device area in the semiconductor material. Higher 24 concentrations of HF tend to initiate an unwanted relatively low level of uniform anodic etching of the entire exposed 26 surface of the semiconductor material with the result that 27 the etch pits denoting the electrically active de~ects are FI 9-75-058 -2- ; ~
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1 less clearly distinguishable by visual inspection than in the 2 case where no back~round etching is produced. Higher potential 3 differences cause unwanted etch pits to appear denoting the 4 presence of inconsequential electrically active defects lying below the active device area. The defect count is a reliable 6 predictor of the yield of satis:Eactory semiconductor devices 7 which are later formed in the semiconductor material.
8 Brief Description of the Drawing g FIGURE 1 is a diagramatic sketch of the apparatus employed in the performance of the method of the present 11 invention;
12 FIGURE lA is a plan view of the silicon wafer sho~n in cross-13 section in Fig. l; and 14 FIGURE 2 is an out-of-scale enlargement of a portion of the silicon wafer of Fig. 1.
16 Description of the Preferred Embodiment 17 Referring to Figure 1, semiconductor wafer 1 is sealed 18 to the opening 2 of synthetic resin polymer cup 3 by O ring 4.
19 Wafer 1 is supported against O ring 4 by stainless steel fixture 5. Cup 3 is filled with HF electrolyte 6 in which 21 is immersed platinum foil 7. Power supply 8 provides a 22 potential difference which is applied between foil 7 and 23 fixture 5, making foil 7 negative with respect to fixture S.
24 Only the surface portion of wafer 1 interior to O ring 4 is contacted by electrolyte 6. Different surface portions 26 of wafer 1 may be exposed at different times to electrolyte 6 27 in order to obtain defect data across the Eace of the wafer.
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1 As indicated in Fig. lA, three separated surface regions 9, 10, 2 and 11 are anodically etehed at successive times. Alternatively, 3 the entire wafer may be anodieally etched at one time by 4 increasing the size of the opening 2 of cup 3. The number of and si~es of the etched surface areas of wafer 1 is not 6 a critical aspect of the present invention.
7 Examining semiconductor wafer 1 in more detail with the 8 aid of Figure 2, wafer 1 comprises a P substrate 12 into g whieh N+ subcollector 13 is diffused. N epitaxial layer 15 is deposited over the surface of substrate 12 under conditions 11 which permit subcolleetor 13 to ~iffuse partially into it.
12 - Eleetrieally aetive defeet 16 extends from subcolleetor 13 13 to the surfaee of epitaxial layer 15 which is in eontact with 14 eleetrolyte 6. Defeet 16 is typical of those which adversely L5 effect device yield in that defect 16 will present a conductive 16 pathway from the eolleetor through a P+ base region to the 17 emitter of a transistor (not shown) whieh is later formed 18 in the epitaxial layer above subeolleetor 13 by subsequent 19 processing steps. Eleetrieally aetive defeet 16 aets as a souree of holes in N type epitaxial layer 15. Said holes 21 migrate toward the overlying surfaee of epitaxial layer 15 22 under the influenee of the eleetric field extending aeross 23 the depletion region generated within epitaxial layer 15 24 by the potential differenee applied between eleetrolyte -6 and substrate 12. As a rbsult of the migration of the holes FI 9-75-058 -4~
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1~69ZZ~l 1 to the surface of epitaxial laye~ 15 and into contact with 2 electrolyte 6, a pit 17 is etched into the surface of epitaxial 3 layer 15 directly over the location of defect 16. There being 4 no significant source of holes elsewhere within N type epi~
taxial layer 15 except at the s.ites of defects such as deect 6 16, there is no other silicon erosion.
7 Anodic processing of silicon wafers in HF solutions has 8 been employed previously to form porous silicon for device g isolation, for electro polishing, and for wafer thinning.
Such applications, in common with the defect detection method 11 of the present invention, involve the dissoluti.on of silicon ,12 by an electro chemical reaction which requires~the presence .
~13 or introduction:o:f~holes. It is'believed that the initiation 14 ~iof silicon dissolution is hole (e ) dependent, in~.ac¢ordance ,15 with the expression Si.t 2HF + (2-n) e ~ Si F2,,+ 2H ~+-~:
16 ne where n < 2.
17 In N type silicon where holes are minority carriers,~
18 enhanced electr,o.chemical etching will occur wher.e~er holes l9 -are inj,ected. ~Eleatrically active defect :sites ac-t as:re~
.~20 combi~ation-gqnera..tiion::,centers,in the N.type-.silicon and ,~21 ~provideiithis hol,e~in.jection on a::localized:basi,s tolprQd;uce~ , -:~22 theietch pit,-~such~:as~pit 17, discussed aboye.i .Such~-etch~p!its 3 a~e7most easi.Ly.s.e.en whe,n.the concentration~oi.the.E~F iniithe~
~a4 ~-ele~c~olyte s~lu~tiQ~ 6;is less than akQut 15~ Concentrations ~ -`- . :
~5 .-.of about S~i;a]~eipreferred. .Evidence has beenl:obtained that . .-,.. ..
6 theleitch~.pits,/deno~tiing,:the presenc~ .Qf elect~ically,acti,ve .,.
~7 ~defe~ts-are llss. clearl~y distinguished:by~,viis~al.examination ::~
; :' ' ' FI 9-75-058 ' -5~
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1 when the concentration of the HF is increased abo~e about 15~.
2 It is believed that such increased concentrations of ~P
3 initiate anodic etching of the silicon surface in accordance 4 with the above-described electro chemical reaction in the presence of randomly distributed hole sources at the surface 6 of wafer 1 due to unwanted impurities, surface states, dan~ling 7 bonds, excessive surface illumination, and the like. The 8 last-named silicon surface conditions, in the presence of 9 increased HF concentrations, cause the appearance of a surface "haze" due to a low level anodic etching reaction which tends 11 to obscure the presence of the etch pits designat-ing the 12 presence of the electrically active defects which are of 13 interest in accordance with the present invention. However, 14 when the HF concentration of the electrolyte solution 6 is set below about 15%, the surface "haze" effect is minimized or 16 eliminated.
17 It can be seen that not all electrically active defects 18 are of consequence in terms of device yield. Those electrically 19 active defects which lie below the active device area in the silicon wafer in most cases will not adversely effect the~
21 performance of the semiconductor devices (bipolar transistors,;~
22 etc.) which are later formed in the active device area of the 23 wafer. In accordance with the method of the present invention, 24 etch pits~are avoided with respect to electrically active 25 defects lying below th~e active device area of the wafer by -~
26 setting the amplitude~of the potential applied between the 27 electrolyte 6 and the wafer 1 so that the width of the ~
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1 depletion region produced within wafer 1 is commensurate with 2 the depth of the active device area, i.e., the depth af the 3 collector-base junction of the vertical bipolar transistors 4 to be formed in wafer 1. Consequently, electrically active defects lying below the base region in epitaxial layer 15 6 within substrate 12 lie below the depletion region so that 7 any holes injected thereby experience no significant electric 8 field and are not driven to the surface of epitaxial layer lS.
g In the absence of holes at the surface of epitaxial layer 15, 10- no etch pits are developed corresponding to electrically 11 active defects lying below the active device region of the 12 silicon wafer which is the desired result.
13 Upon the completion of the anodic etching method of 14 the present invention, wafer 1 is removed from the apparatus 1`5 of Fig. 1 and visually examined by any convenient technique 16 such as microscope inspection, infrared TV camera and monitor, 17 etc. The presence of one or more etch pits within a known 18 critical surface area of wafer 1 is a reliable predictor 19 that any device later formed within that critical area will be unacceptable. Alternatively, the number of etch pits per 21- square surface area has been found to correlate closely with 22 device yield. The anodically etched wafer surface areas may 23 be predetermined portions o actual product wafers or the anodic 24 etching may be done on test wafers which had been subjected to ; ~;
the same processing steps as the product wafers. In either 26 event, the appearance of etch pits in critical wafer surface -27 areas or in excess of an allowable surface area density (count) ,' ' :, FI 9-75-058 -7- ~ ;
. .
~ ,...
- : ' :.
~69'~Z~ ~
1 reliably establishes that the wafers tested and all those 2 which are untested but fabricated with the same process 3 steps as the tested wafers will not yield good devices.
4 Accordingly, those further costly but futile manu$acturing steps ordinarily required to complete the desired devices in 6 the tested wafers ara not undertaken thus minimizing the 7 fabrication investment in material that in any event would 8 be scrapped eventually.
9 While the invention has been partic~larly shown and described with reference to the preferred embodiment thereof, 11 it will be understood by those skilled in the art that various - 12 changes in form and details may be made therein without 13 departing from the spirit and scope of the invention.
14 , `
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Summar~ of the Invention 11 Electrically active defects a`re detected in N type 12 silicon substrates and epitaxial layers by the anodic 13 etching of the semiconductor material exposed to a hydro-14 fluoric acid solution. In order to enhance the visual 15 discrimination between electrically~active defects and non- ;
16 electrically active defects (which do not affect device yield), 17 it is preferable that the concentration of the HF solution 18 employed be less than about 15~ and that the potential 19 difference between the solution and the semiconductor material be set so that the width of the resulting depletion layer 21 below the surface of the semiconductor material in contact 22 with the solution is commensurate with the depth of the 23 active device area in the semiconductor material. Higher 24 concentrations of HF tend to initiate an unwanted relatively low level of uniform anodic etching of the entire exposed 26 surface of the semiconductor material with the result that 27 the etch pits denoting the electrically active de~ects are FI 9-75-058 -2- ; ~
-.:
~: ~
.,. .. . . . . . . ~ . . ... .. . . .
Z;2~L
1 less clearly distinguishable by visual inspection than in the 2 case where no back~round etching is produced. Higher potential 3 differences cause unwanted etch pits to appear denoting the 4 presence of inconsequential electrically active defects lying below the active device area. The defect count is a reliable 6 predictor of the yield of satis:Eactory semiconductor devices 7 which are later formed in the semiconductor material.
8 Brief Description of the Drawing g FIGURE 1 is a diagramatic sketch of the apparatus employed in the performance of the method of the present 11 invention;
12 FIGURE lA is a plan view of the silicon wafer sho~n in cross-13 section in Fig. l; and 14 FIGURE 2 is an out-of-scale enlargement of a portion of the silicon wafer of Fig. 1.
16 Description of the Preferred Embodiment 17 Referring to Figure 1, semiconductor wafer 1 is sealed 18 to the opening 2 of synthetic resin polymer cup 3 by O ring 4.
19 Wafer 1 is supported against O ring 4 by stainless steel fixture 5. Cup 3 is filled with HF electrolyte 6 in which 21 is immersed platinum foil 7. Power supply 8 provides a 22 potential difference which is applied between foil 7 and 23 fixture 5, making foil 7 negative with respect to fixture S.
24 Only the surface portion of wafer 1 interior to O ring 4 is contacted by electrolyte 6. Different surface portions 26 of wafer 1 may be exposed at different times to electrolyte 6 27 in order to obtain defect data across the Eace of the wafer.
` ' ~ ' .
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1 As indicated in Fig. lA, three separated surface regions 9, 10, 2 and 11 are anodically etehed at successive times. Alternatively, 3 the entire wafer may be anodieally etched at one time by 4 increasing the size of the opening 2 of cup 3. The number of and si~es of the etched surface areas of wafer 1 is not 6 a critical aspect of the present invention.
7 Examining semiconductor wafer 1 in more detail with the 8 aid of Figure 2, wafer 1 comprises a P substrate 12 into g whieh N+ subcollector 13 is diffused. N epitaxial layer 15 is deposited over the surface of substrate 12 under conditions 11 which permit subcolleetor 13 to ~iffuse partially into it.
12 - Eleetrieally aetive defeet 16 extends from subcolleetor 13 13 to the surfaee of epitaxial layer 15 which is in eontact with 14 eleetrolyte 6. Defeet 16 is typical of those which adversely L5 effect device yield in that defect 16 will present a conductive 16 pathway from the eolleetor through a P+ base region to the 17 emitter of a transistor (not shown) whieh is later formed 18 in the epitaxial layer above subeolleetor 13 by subsequent 19 processing steps. Eleetrieally aetive defeet 16 aets as a souree of holes in N type epitaxial layer 15. Said holes 21 migrate toward the overlying surfaee of epitaxial layer 15 22 under the influenee of the eleetric field extending aeross 23 the depletion region generated within epitaxial layer 15 24 by the potential differenee applied between eleetrolyte -6 and substrate 12. As a rbsult of the migration of the holes FI 9-75-058 -4~
,. ,, ', ' ~
..
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1~69ZZ~l 1 to the surface of epitaxial laye~ 15 and into contact with 2 electrolyte 6, a pit 17 is etched into the surface of epitaxial 3 layer 15 directly over the location of defect 16. There being 4 no significant source of holes elsewhere within N type epi~
taxial layer 15 except at the s.ites of defects such as deect 6 16, there is no other silicon erosion.
7 Anodic processing of silicon wafers in HF solutions has 8 been employed previously to form porous silicon for device g isolation, for electro polishing, and for wafer thinning.
Such applications, in common with the defect detection method 11 of the present invention, involve the dissoluti.on of silicon ,12 by an electro chemical reaction which requires~the presence .
~13 or introduction:o:f~holes. It is'believed that the initiation 14 ~iof silicon dissolution is hole (e ) dependent, in~.ac¢ordance ,15 with the expression Si.t 2HF + (2-n) e ~ Si F2,,+ 2H ~+-~:
16 ne where n < 2.
17 In N type silicon where holes are minority carriers,~
18 enhanced electr,o.chemical etching will occur wher.e~er holes l9 -are inj,ected. ~Eleatrically active defect :sites ac-t as:re~
.~20 combi~ation-gqnera..tiion::,centers,in the N.type-.silicon and ,~21 ~provideiithis hol,e~in.jection on a::localized:basi,s tolprQd;uce~ , -:~22 theietch pit,-~such~:as~pit 17, discussed aboye.i .Such~-etch~p!its 3 a~e7most easi.Ly.s.e.en whe,n.the concentration~oi.the.E~F iniithe~
~a4 ~-ele~c~olyte s~lu~tiQ~ 6;is less than akQut 15~ Concentrations ~ -`- . :
~5 .-.of about S~i;a]~eipreferred. .Evidence has beenl:obtained that . .-,.. ..
6 theleitch~.pits,/deno~tiing,:the presenc~ .Qf elect~ically,acti,ve .,.
~7 ~defe~ts-are llss. clearl~y distinguished:by~,viis~al.examination ::~
; :' ' ' FI 9-75-058 ' -5~
-692Z~
1 when the concentration of the HF is increased abo~e about 15~.
2 It is believed that such increased concentrations of ~P
3 initiate anodic etching of the silicon surface in accordance 4 with the above-described electro chemical reaction in the presence of randomly distributed hole sources at the surface 6 of wafer 1 due to unwanted impurities, surface states, dan~ling 7 bonds, excessive surface illumination, and the like. The 8 last-named silicon surface conditions, in the presence of 9 increased HF concentrations, cause the appearance of a surface "haze" due to a low level anodic etching reaction which tends 11 to obscure the presence of the etch pits designat-ing the 12 presence of the electrically active defects which are of 13 interest in accordance with the present invention. However, 14 when the HF concentration of the electrolyte solution 6 is set below about 15%, the surface "haze" effect is minimized or 16 eliminated.
17 It can be seen that not all electrically active defects 18 are of consequence in terms of device yield. Those electrically 19 active defects which lie below the active device area in the silicon wafer in most cases will not adversely effect the~
21 performance of the semiconductor devices (bipolar transistors,;~
22 etc.) which are later formed in the active device area of the 23 wafer. In accordance with the method of the present invention, 24 etch pits~are avoided with respect to electrically active 25 defects lying below th~e active device area of the wafer by -~
26 setting the amplitude~of the potential applied between the 27 electrolyte 6 and the wafer 1 so that the width of the ~
!
- FI 9-75-058 -6- ~ ~
. . , ~ .
, ~ :
':
.. ~:
, .
.
~il6~3Z2~
1 depletion region produced within wafer 1 is commensurate with 2 the depth of the active device area, i.e., the depth af the 3 collector-base junction of the vertical bipolar transistors 4 to be formed in wafer 1. Consequently, electrically active defects lying below the base region in epitaxial layer 15 6 within substrate 12 lie below the depletion region so that 7 any holes injected thereby experience no significant electric 8 field and are not driven to the surface of epitaxial layer lS.
g In the absence of holes at the surface of epitaxial layer 15, 10- no etch pits are developed corresponding to electrically 11 active defects lying below the active device region of the 12 silicon wafer which is the desired result.
13 Upon the completion of the anodic etching method of 14 the present invention, wafer 1 is removed from the apparatus 1`5 of Fig. 1 and visually examined by any convenient technique 16 such as microscope inspection, infrared TV camera and monitor, 17 etc. The presence of one or more etch pits within a known 18 critical surface area of wafer 1 is a reliable predictor 19 that any device later formed within that critical area will be unacceptable. Alternatively, the number of etch pits per 21- square surface area has been found to correlate closely with 22 device yield. The anodically etched wafer surface areas may 23 be predetermined portions o actual product wafers or the anodic 24 etching may be done on test wafers which had been subjected to ; ~;
the same processing steps as the product wafers. In either 26 event, the appearance of etch pits in critical wafer surface -27 areas or in excess of an allowable surface area density (count) ,' ' :, FI 9-75-058 -7- ~ ;
. .
~ ,...
- : ' :.
~69'~Z~ ~
1 reliably establishes that the wafers tested and all those 2 which are untested but fabricated with the same process 3 steps as the tested wafers will not yield good devices.
4 Accordingly, those further costly but futile manu$acturing steps ordinarily required to complete the desired devices in 6 the tested wafers ara not undertaken thus minimizing the 7 fabrication investment in material that in any event would 8 be scrapped eventually.
9 While the invention has been partic~larly shown and described with reference to the preferred embodiment thereof, 11 it will be understood by those skilled in the art that various - 12 changes in form and details may be made therein without 13 departing from the spirit and scope of the invention.
14 , `
. ~ .,`'~
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.
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Claims (7)
1. The method comprising providing N type silicon material containing active device areas of known depth below a surface of said material, contacting said surface of said material with a hydro-flouric acid solution of concentration less than about 15%, applying a potential difference between said solution and said material making said solution negative with respect to said material, the amplitude of said potential difference being set so that a depletion region is created below said surface of said material having a width commensurate with said depth of said active device areas, and visually examining said surface of said wafer for etch pits.
2. The method defined in Claim 1 wherein said con-centration is about 5%.
3. The method defined in Claim 1 wherein a vertical bipolar transistor is to be later formed in said silicon material and said width of said depletion layer is commen-surate with the depth of the collector-base junction of said transistor.
4. The method defined in Claim 1 wherein said silicon material is a test wafer representing a number of product wafers, said test wafer and said product wafers being fab-ricated by the same processing steps.
5. The method defined in Claim 1 wherein said silicon material is a product wafer and said solution contacts only a portion of said surface of said wafer.
6. The method defined in Claim 1 and further including counting the number of said etch pits per square surface area.
7. The method defined in Claim 1 and further including determining whether any of said etch pits are located in a critical surface area of said silicon material.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US66723276A | 1976-03-15 | 1976-03-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1069221A true CA1069221A (en) | 1980-01-01 |
Family
ID=24677379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA272,839A Expired CA1069221A (en) | 1976-03-15 | 1977-02-28 | Anodic etching method for the detection of electrically active defects in silicon |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS52111373A (en) |
| CA (1) | CA1069221A (en) |
| DE (1) | DE2707372C2 (en) |
| FR (1) | FR2344847A1 (en) |
| GB (1) | GB1514697A (en) |
| IT (1) | IT1118013B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2532760A1 (en) * | 1982-09-08 | 1984-03-09 | Comp Generale Electricite | METHOD AND DEVICE FOR OBTAINING PHYSICAL CHARACTERISTICS OF A SEMICONDUCTOR MATERIAL |
| JPS6066920A (en) * | 1983-09-22 | 1985-04-17 | 北興化工機株式会社 | Conveyable silage vessel |
| DE59010140D1 (en) * | 1989-05-31 | 1996-03-28 | Siemens Ag | Method for large-area electrical contacting of a semiconductor crystal body with the help of electrolytes |
| DE3917702A1 (en) * | 1989-05-31 | 1990-12-06 | Siemens Ag | METHOD FOR DETERMINING THE DIFFERENTIAL LENGTH OF MINORITY CHARGE CARRIERS IN A SEMICONDUCTOR CRYSTAL BODY BY MEANS OF AN ELECTROLYTIC CELL |
| EP0400386B1 (en) * | 1989-05-31 | 1994-08-24 | Siemens Aktiengesellschaft | Process for determining the recombination velocity of minority charges at the borders between semiconductors and other substances |
| DE4328083A1 (en) * | 1993-08-20 | 1994-03-31 | Ignaz Eisele | Microscopic measuring of surface topography and potential distribution - laterally displacing field effect structure relative to scanned surface |
| JP4916249B2 (en) * | 2006-08-10 | 2012-04-11 | 新電元工業株式会社 | Inspection method of semiconductor substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3655540A (en) * | 1970-06-22 | 1972-04-11 | Bell Telephone Labor Inc | Method of making semiconductor device components |
| US3902979A (en) * | 1974-06-24 | 1975-09-02 | Westinghouse Electric Corp | Insulator substrate with a thin mono-crystalline semiconductive layer and method of fabrication |
-
1977
- 1977-01-18 FR FR7702072A patent/FR2344847A1/en active Granted
- 1977-02-21 DE DE19772707372 patent/DE2707372C2/en not_active Expired
- 1977-02-24 GB GB782177A patent/GB1514697A/en not_active Expired
- 1977-02-25 IT IT2066677A patent/IT1118013B/en active
- 1977-02-25 JP JP1940477A patent/JPS52111373A/en active Granted
- 1977-02-28 CA CA272,839A patent/CA1069221A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2344847B1 (en) | 1979-09-28 |
| IT1118013B (en) | 1986-02-24 |
| JPS5320380B2 (en) | 1978-06-26 |
| FR2344847A1 (en) | 1977-10-14 |
| DE2707372A1 (en) | 1977-09-22 |
| GB1514697A (en) | 1978-06-21 |
| JPS52111373A (en) | 1977-09-19 |
| DE2707372C2 (en) | 1985-08-22 |
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