CA1049157A - Fet device with reduced overlap capacitance and method of manufacture - Google Patents

Fet device with reduced overlap capacitance and method of manufacture

Info

Publication number
CA1049157A
CA1049157A CA76254958A CA254958A CA1049157A CA 1049157 A CA1049157 A CA 1049157A CA 76254958 A CA76254958 A CA 76254958A CA 254958 A CA254958 A CA 254958A CA 1049157 A CA1049157 A CA 1049157A
Authority
CA
Canada
Prior art keywords
diffused
insulating layer
substrate
layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA76254958A
Other languages
English (en)
French (fr)
Inventor
Ronald P. Esch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1049157A publication Critical patent/CA1049157A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
CA76254958A 1975-06-30 1976-06-16 Fet device with reduced overlap capacitance and method of manufacture Expired CA1049157A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59199575A 1975-06-30 1975-06-30

Publications (1)

Publication Number Publication Date
CA1049157A true CA1049157A (en) 1979-02-20

Family

ID=24368826

Family Applications (1)

Application Number Title Priority Date Filing Date
CA76254958A Expired CA1049157A (en) 1975-06-30 1976-06-16 Fet device with reduced overlap capacitance and method of manufacture

Country Status (6)

Country Link
JP (1) JPS5228276A (it)
CA (1) CA1049157A (it)
DE (1) DE2621765A1 (it)
FR (1) FR2316745A1 (it)
GB (1) GB1521625A (it)
IT (1) IT1063563B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52112199A (en) * 1976-03-17 1977-09-20 Kyoei Kikou Kk Automatic fastening tool

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899372A (en) * 1973-10-31 1975-08-12 Ibm Process for controlling insulating film thickness across a semiconductor wafer

Also Published As

Publication number Publication date
FR2316745B1 (it) 1980-09-26
JPS5228276A (en) 1977-03-03
IT1063563B (it) 1985-02-11
GB1521625A (en) 1978-08-16
FR2316745A1 (fr) 1977-01-28
DE2621765A1 (de) 1977-01-20

Similar Documents

Publication Publication Date Title
US4287661A (en) Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US3983620A (en) Self-aligned CMOS process for bulk silicon and insulating substrate device
EP0083785B1 (en) Method of forming self-aligned field effect transistors in integrated circuit structures
US4523213A (en) MOS Semiconductor device and method of manufacturing the same
CA1120609A (en) Method for forming a narrow dimensioned mask opening on a silicon body
US5438009A (en) Method of fabrication of MOSFET device with buried bit line
KR100242352B1 (ko) 반도체 장치를 위한 자기 정합 컨택트홀의 제조방법
US4251571A (en) Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
JP3318074B2 (ja) コンタクトを含む半導体デバイスとその製造方法
CA1203323A (en) Method of providing a narrow groove or slot in a substrate region, in particular a semiconductor substrate region
US4191603A (en) Making semiconductor structure with improved phosphosilicate glass isolation
US4305760A (en) Polysilicon-to-substrate contact processing
US4374454A (en) Method of manufacturing a semiconductor device
US4413401A (en) Method for making a semiconductor capacitor
EP0162774B1 (en) Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby
US4053349A (en) Method for forming a narrow gap
JPS6249750B2 (it)
US3986896A (en) Method of manufacturing semiconductor devices
US5275960A (en) Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength
US4450021A (en) Mask diffusion process for forming Zener diode or complementary field effect transistors
US4169270A (en) Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
US4047284A (en) Self-aligned CMOS process for bulk silicon and insulating substrate device
US4290186A (en) Method of making integrated semiconductor structure having an MOS and a capacitor device
US4069577A (en) Method of making a semiconductor device
US4610078A (en) Method of making high density dielectric isolated gate MOS transistor