CA1049157A - Fet device with reduced overlap capacitance and method of manufacture - Google Patents

Fet device with reduced overlap capacitance and method of manufacture

Info

Publication number
CA1049157A
CA1049157A CA76254958A CA254958A CA1049157A CA 1049157 A CA1049157 A CA 1049157A CA 76254958 A CA76254958 A CA 76254958A CA 254958 A CA254958 A CA 254958A CA 1049157 A CA1049157 A CA 1049157A
Authority
CA
Canada
Prior art keywords
diffused
insulating layer
substrate
layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA76254958A
Other languages
English (en)
French (fr)
Inventor
Ronald P. Esch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1049157A publication Critical patent/CA1049157A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D64/011
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
CA76254958A 1975-06-30 1976-06-16 Fet device with reduced overlap capacitance and method of manufacture Expired CA1049157A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59199575A 1975-06-30 1975-06-30

Publications (1)

Publication Number Publication Date
CA1049157A true CA1049157A (en) 1979-02-20

Family

ID=24368826

Family Applications (1)

Application Number Title Priority Date Filing Date
CA76254958A Expired CA1049157A (en) 1975-06-30 1976-06-16 Fet device with reduced overlap capacitance and method of manufacture

Country Status (6)

Country Link
JP (1) JPS5228276A (OSRAM)
CA (1) CA1049157A (OSRAM)
DE (1) DE2621765A1 (OSRAM)
FR (1) FR2316745A1 (OSRAM)
GB (1) GB1521625A (OSRAM)
IT (1) IT1063563B (OSRAM)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52112199A (en) * 1976-03-17 1977-09-20 Kyoei Kikou Kk Automatic fastening tool

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899372A (en) * 1973-10-31 1975-08-12 Ibm Process for controlling insulating film thickness across a semiconductor wafer

Also Published As

Publication number Publication date
FR2316745A1 (fr) 1977-01-28
FR2316745B1 (OSRAM) 1980-09-26
IT1063563B (it) 1985-02-11
DE2621765A1 (de) 1977-01-20
JPS5228276A (en) 1977-03-03
GB1521625A (en) 1978-08-16

Similar Documents

Publication Publication Date Title
US3983620A (en) Self-aligned CMOS process for bulk silicon and insulating substrate device
EP0083785B1 (en) Method of forming self-aligned field effect transistors in integrated circuit structures
US4523213A (en) MOS Semiconductor device and method of manufacturing the same
CA1120609A (en) Method for forming a narrow dimensioned mask opening on a silicon body
US5438009A (en) Method of fabrication of MOSFET device with buried bit line
KR100242352B1 (ko) 반도체 장치를 위한 자기 정합 컨택트홀의 제조방법
US4251571A (en) Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
JP3318074B2 (ja) コンタクトを含む半導体デバイスとその製造方法
US4103415A (en) Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
CA1203323A (en) Method of providing a narrow groove or slot in a substrate region, in particular a semiconductor substrate region
US4191603A (en) Making semiconductor structure with improved phosphosilicate glass isolation
US4305760A (en) Polysilicon-to-substrate contact processing
US4374454A (en) Method of manufacturing a semiconductor device
US4413401A (en) Method for making a semiconductor capacitor
EP0162774B1 (en) Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby
JPS6249750B2 (OSRAM)
US4053349A (en) Method for forming a narrow gap
US3986896A (en) Method of manufacturing semiconductor devices
US5275960A (en) Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength
US4450021A (en) Mask diffusion process for forming Zener diode or complementary field effect transistors
US4169270A (en) Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
US4047284A (en) Self-aligned CMOS process for bulk silicon and insulating substrate device
US4290186A (en) Method of making integrated semiconductor structure having an MOS and a capacitor device
US4069577A (en) Method of making a semiconductor device
US4610078A (en) Method of making high density dielectric isolated gate MOS transistor