CA1043420A - Input supply independent circuit - Google Patents
Input supply independent circuitInfo
- Publication number
- CA1043420A CA1043420A CA232,980A CA232980A CA1043420A CA 1043420 A CA1043420 A CA 1043420A CA 232980 A CA232980 A CA 232980A CA 1043420 A CA1043420 A CA 1043420A
- Authority
- CA
- Canada
- Prior art keywords
- transistors
- emitter
- base
- pair
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Abstract
Application for Patent of Robert C. Dobkin for INPUT SUPPLY INDEPENDENT CIRCUIT
ABSTRACT OF THE DISCLOSURE
A circuit includes a plurality of transistors which are biased by a supply to provide an output which is independent of that supply and dependent only on the summation of the base-emitter voltages of the transistors, if any. A first pair of transistors are connected in series with one another between the supply and a second pair of transistors are connected in series with one another between the supply. The base-emitter junctions of the transistors are connected in a series loop, such that a voltage is developed between the base-emitter junc-tions of two adjacent transistors which is equal to the base-emitter voltage summation. The base-emitter voltages of any series connected transistors oppose one another in the series loop. Since the collector currents of the series connected transistors are equal to one another and their base-emitter voltages oppose one another in the series loop, the base-emitter voltage summation will be independent of collector currents and, therefore, independent of the input supply. The circuit can be employed as either a voltage or current regulator. As a regu-lator circuit, the emitter area of one transistor is different than the emitter area of another transistor, such that the sum-mation of the base-emitter voltages will be other than zero and independent of the input supply. The circuit can also be em-ployed as a buffer amplifier by making the emitter areas of the transistors equal to one another.
ABSTRACT OF THE DISCLOSURE
A circuit includes a plurality of transistors which are biased by a supply to provide an output which is independent of that supply and dependent only on the summation of the base-emitter voltages of the transistors, if any. A first pair of transistors are connected in series with one another between the supply and a second pair of transistors are connected in series with one another between the supply. The base-emitter junctions of the transistors are connected in a series loop, such that a voltage is developed between the base-emitter junc-tions of two adjacent transistors which is equal to the base-emitter voltage summation. The base-emitter voltages of any series connected transistors oppose one another in the series loop. Since the collector currents of the series connected transistors are equal to one another and their base-emitter voltages oppose one another in the series loop, the base-emitter voltage summation will be independent of collector currents and, therefore, independent of the input supply. The circuit can be employed as either a voltage or current regulator. As a regu-lator circuit, the emitter area of one transistor is different than the emitter area of another transistor, such that the sum-mation of the base-emitter voltages will be other than zero and independent of the input supply. The circuit can also be em-ployed as a buffer amplifier by making the emitter areas of the transistors equal to one another.
Description
1. \ 1043~Z0 1 ¦ BAC~GROU~D OF T~IE INVENTION
I
3 I FIELD O~ THE INVE.NTIO~
4 I This invention relates generally to a circuit having an I
h 5 I output which is ~h~ oo~ of its input supply, and more par-6 ¦ticularly to such a circuit in which a voltage related to the - 7 ¦output voltage thereof is developed which is proportional only 8 ¦to the difference of the emitter areas o~ transistors.
.~ 9 l PRIOR ART
11 Various types of circuits require an output which is 12 independent of the input voltage or current supply. It has 13 been the usual practice in the past to isolate the output of 14 such circuits from the input supply with a relatively large number of components. This practice has resulted in relatively 16 large and complex circuits. Since the cost of an integrated 17 circuit is related to the nùmber of components contained therein 18 and to the complexity thereof, it is desirable to reduce the l9 number of components required to produce a particular result to a minimum. Furthermore, the operation of such circuits is 21 subject to processing parameters, rather than solely to basic 22 transistor parameters, and such processing parameters are not 23 easily controlled.
24 A good example of a circuit which requires its output to be independent of its input supply is a regulator circuit.
26 A high degree of current or voltage regulation in inte~rated 27 circuits has required relatively complex circuits in the past.
28 For example, a Zener diode voltage regulator requires several 29 stages of current amplification to reduce the dynamic impedance of the circuit to provide a well regulated voltage supply output.
A relatively large number of components is required to provide 3 the desired amount of current amplification and to decrease
I
3 I FIELD O~ THE INVE.NTIO~
4 I This invention relates generally to a circuit having an I
h 5 I output which is ~h~ oo~ of its input supply, and more par-6 ¦ticularly to such a circuit in which a voltage related to the - 7 ¦output voltage thereof is developed which is proportional only 8 ¦to the difference of the emitter areas o~ transistors.
.~ 9 l PRIOR ART
11 Various types of circuits require an output which is 12 independent of the input voltage or current supply. It has 13 been the usual practice in the past to isolate the output of 14 such circuits from the input supply with a relatively large number of components. This practice has resulted in relatively 16 large and complex circuits. Since the cost of an integrated 17 circuit is related to the nùmber of components contained therein 18 and to the complexity thereof, it is desirable to reduce the l9 number of components required to produce a particular result to a minimum. Furthermore, the operation of such circuits is 21 subject to processing parameters, rather than solely to basic 22 transistor parameters, and such processing parameters are not 23 easily controlled.
24 A good example of a circuit which requires its output to be independent of its input supply is a regulator circuit.
26 A high degree of current or voltage regulation in inte~rated 27 circuits has required relatively complex circuits in the past.
28 For example, a Zener diode voltage regulator requires several 29 stages of current amplification to reduce the dynamic impedance of the circuit to provide a well regulated voltage supply output.
A relatively large number of components is required to provide 3 the desired amount of current amplification and to decrease
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~," ' . . `' , , ': , ' , , . , ' ' . ` ' 10434'~0 the dynamic impendance sufficiently to provide such a regulated S~lpply .
Another type of circuit which requires its output to be independent of its input supply is a buffer amplifier. In a buffer amplifier, such as a voltage follower or current amp-lifier, it is desirable to have the voltage of the input signal source reflected exactly at the output, with a relatively hiqh impedance input and low impedance output. If the output of such an amplifier is not independent of its input supply, varia-tions in that supply will affect the output and the input volt-age will not be reflected exactly at such output. Furthermore, if such output is dependent upon processing parameters, rather than solely on basic transistor parameters, the output cannot i be well defined~
Accordingly, it can be appreciated that a need exists -for a circuit which will provide an output which is independent of its voltage or current supply without being relatively com-plex, requiring a large number of components, and which is in-dependent of processing parameters. More particularly, a need exists for such a circuit which is formed of relatively few components and is dependent only on basic transistor parameters --for its operation, which parameters are capable of being con- -trolled within relatively close tolerances. ~ -' -.' .... ,- .:, .
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1~)43420 This invention relates to a circuit disposed for connection to an input supply for providing ~n output which is independent of that supply, comprising a p~urality of transistors, and means responsive to the input supply for generating a base-emitter voltage on all of the transistors. The base-emitter junctions of the transistors are connected serially in a loop with one~ another, such that the summation of the base-emitter voltages of the transistors is developed as an output voltage between the base-emitter junctions of two adjacent ones of the transistors in the loop. The collector currents o~ any of the transistors having their collector-emitter circuits connected in series are equal to one another and their base-emitter volt-ages oppose one another around the loop, such that the summation of thebase-emitter voltages is independent of the collector currents of the transistors and only proportional to the 16 difference of the emitter areas of the transistors.
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-A resistor may be provided in any one of the emitter circuits of the transistors, such that various output characteristics can be obtained.
The invention, however, as well as the features and advantages thereof will be more fully realized and understood from the following detailed descript.ion, when taken in con-junction with the accompanying drawings, wherein:
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a circuit diagram of a four terminal network constructed in accordance with the principles of the present invention.
Figure 2 is a circuit diagram of an alternate embodiment of the four terminal network of the present invention.
Figure 3 is a circuit diagram of a current regulator constructed in accordance with the principles of the present :~-invention.
Figure 4 is a circuit diagram of a voltage regulator constructed in accordance with the principles of the present invention.
Figure 5 is a circuit diagram of a buffer amplifier constructed in accordance with the principles of the present -invention.
~ 5 .., ,. 1 10434Zo 2 ¦ DETAILED DESCRIPTION OF TIIE PREI~ERRED E~IBODIME~TS
.~ , .
~," ' . . `' , , ': , ' , , . , ' ' . ` ' 10434'~0 the dynamic impendance sufficiently to provide such a regulated S~lpply .
Another type of circuit which requires its output to be independent of its input supply is a buffer amplifier. In a buffer amplifier, such as a voltage follower or current amp-lifier, it is desirable to have the voltage of the input signal source reflected exactly at the output, with a relatively hiqh impedance input and low impedance output. If the output of such an amplifier is not independent of its input supply, varia-tions in that supply will affect the output and the input volt-age will not be reflected exactly at such output. Furthermore, if such output is dependent upon processing parameters, rather than solely on basic transistor parameters, the output cannot i be well defined~
Accordingly, it can be appreciated that a need exists -for a circuit which will provide an output which is independent of its voltage or current supply without being relatively com-plex, requiring a large number of components, and which is in-dependent of processing parameters. More particularly, a need exists for such a circuit which is formed of relatively few components and is dependent only on basic transistor parameters --for its operation, which parameters are capable of being con- -trolled within relatively close tolerances. ~ -' -.' .... ,- .:, .
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1~)43420 This invention relates to a circuit disposed for connection to an input supply for providing ~n output which is independent of that supply, comprising a p~urality of transistors, and means responsive to the input supply for generating a base-emitter voltage on all of the transistors. The base-emitter junctions of the transistors are connected serially in a loop with one~ another, such that the summation of the base-emitter voltages of the transistors is developed as an output voltage between the base-emitter junctions of two adjacent ones of the transistors in the loop. The collector currents o~ any of the transistors having their collector-emitter circuits connected in series are equal to one another and their base-emitter volt-ages oppose one another around the loop, such that the summation of thebase-emitter voltages is independent of the collector currents of the transistors and only proportional to the 16 difference of the emitter areas of the transistors.
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-A resistor may be provided in any one of the emitter circuits of the transistors, such that various output characteristics can be obtained.
The invention, however, as well as the features and advantages thereof will be more fully realized and understood from the following detailed descript.ion, when taken in con-junction with the accompanying drawings, wherein:
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a circuit diagram of a four terminal network constructed in accordance with the principles of the present invention.
Figure 2 is a circuit diagram of an alternate embodiment of the four terminal network of the present invention.
Figure 3 is a circuit diagram of a current regulator constructed in accordance with the principles of the present :~-invention.
Figure 4 is a circuit diagram of a voltage regulator constructed in accordance with the principles of the present invention.
Figure 5 is a circuit diagram of a buffer amplifier constructed in accordance with the principles of the present -invention.
~ 5 .., ,. 1 10434Zo 2 ¦ DETAILED DESCRIPTION OF TIIE PREI~ERRED E~IBODIME~TS
3 ¦ With reference to Figure 1, there is shown a four ter-
4 ¦ minal net~ork ~hich is constructed in accordance with the prin-
5 ¦ ciples of t~le present invention. A pair of transistors 10 and
6 ¦ 12 have their collector-emitter circt~its connected in serics
7 ¦ with one another between a pair of terminals 14 and 16. A
8 I pair of ~ransistors lS and 20 have their collector-emitter
9 ¦ circuits connected in series ~ith one another between a pair of terminals 22 and 2~. Resistors 26, 28, 30 and 32 are con-11 nected in the e~itter circuits of the transistors 10, 12, 18 12 and 20, respectively. The value of any one or all of the re^
13 sistors 26-32 may be zero. Preferrably, only one of the re-14 sistors 26-32 will have a value other than zero.
It can be appreciated from Figure 1 that ~he base-emitter 16 junctions of the transistors 10, 12, 18 and 20 are connected 17 serially in a loop with one another. That is, beginning with 18 the terminal 16, the loop includes the resistor 28, the base^
emit;er junction of ~he transistor 12, the resistor 30, the base-emitter junction of the transistor 1~, the base-emitter 21 junction of the transistor 10, the resistor 26, the base-emitter 22 junction of the transistor 20, and the resistor 32. If the ~ -23 terminal 16 is connected to the terminal 24 and only one of 24 the resistors 26-32 has a value other than zero, the summation o the base-emitter voltages of the transistors will be developed 26 on that resistor.
27 In the above described serial loop, the base-emitter 28 voltage of the transistor 12 opposses the base-emitter voltage 29 of th0 transistor 10 and the base-emitter voltage of the tran^
sistor 20. Also, the base-emitter voltage of the transistor 20 31 opposes the base^emitter voltage of the transistor 18. Since 32 the transistors 10 and 12 have their collector-emitter circuits ! ~~
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~ lU43~zo l , connected in series, .heir collector currents will be equ~l.
2 It can be appreciated that the collector currents of tlle tran-3 sistors 18 and 20 will also be equal. Accordin~ly, the summa-4 tion of the base-emitter voltages of all of the transistors will be proportional ~o the difference of their emitter areas.
6 Tl;at is, the difference of tl~c base-emitter voltages, ~Vbe, 7 w]lich is the voltage developed across one of the resistors 8 26-32 having a value other than zero, is dofined by the expres-9 sion:
~Vbe ~ Kq ln ~ tl) l2 where Jc is the combined current density of the transistors 13 12 and 18 and Jc is tlle combined current density of the tran-14 sistors 10 and 20. Accordingly, if the emitter areas of the transistors are of different values, the current density ratio 16¦ of the above expressiGn will be other than zero. It can be 17 Iappreciated, therelore, tha~ the voltage of an input source 181 which supplies a bias to each of the transistors 10, 12, 18 19 ¦and 20 will not affect the summation of the base-emitter volt-20 ¦ages, ~Vbe, developed on one of the resistors 26-32 which has -21 ¦a value other than zero. It can also be appreciated that this 22 ¦summation of the base-emitter voltages, ~Vbe, will be zero if `
23 lall of the emitter areas of the transistors aTe equal to one 24 ¦another.
25 ¦ An alternate embodiment of a four terminal network con-26 ¦structed in accordance with the principles of the present in-27 ¦vention is illustrated in Figure 2. As shown therein, tran-28 ¦sistors 34 and 36 are connected in series between a pair of 29 termina~s 42 and 44 and transistors 46 and 48 are connected in series between a pair of terminals S0 and 52. Resistors 54, 31 56, 58 and 60 are connected in the emitter circuits of the tran-32 sistors 34, 36, 46 and 48, respectively. It can be appreciated ,, ,, ., . ., J ~, ~ ' . -7 ~,,., . ,. ' ,........................... .,, , l- '' " .. ., " . . , . ," ., ; .. ... " ,. .. , , , " , ,." .. , , : , ,. .. ,. " " . , . , , ,, .. " ,, " ,. .. .. .... . ....
~ 1~)43420 11 from the drawings and the above description that the circuit 21 thus described in Figure 2 is similar to the circuit ill,ustrated 31 in Figure 1. A transistor 62 has its collector-emitter circuit 41 connected in series bet~Yeen tl~e terminal 50 and the collector 5¦ of the transistor 46 and has its base connected to the terminal 61 42. The transistor 62 isolates the collector of the transistor 7 ¦ 46 from any voltage changes whicll may occur on the ter~ninal 50 8 ¦ and raises the outpu; impedance of the circuit.
9 ¦ With reference to Figure 3, there'is shown a current
13 sistors 26-32 may be zero. Preferrably, only one of the re-14 sistors 26-32 will have a value other than zero.
It can be appreciated from Figure 1 that ~he base-emitter 16 junctions of the transistors 10, 12, 18 and 20 are connected 17 serially in a loop with one another. That is, beginning with 18 the terminal 16, the loop includes the resistor 28, the base^
emit;er junction of ~he transistor 12, the resistor 30, the base-emitter junction of the transistor 1~, the base-emitter 21 junction of the transistor 10, the resistor 26, the base-emitter 22 junction of the transistor 20, and the resistor 32. If the ~ -23 terminal 16 is connected to the terminal 24 and only one of 24 the resistors 26-32 has a value other than zero, the summation o the base-emitter voltages of the transistors will be developed 26 on that resistor.
27 In the above described serial loop, the base-emitter 28 voltage of the transistor 12 opposses the base-emitter voltage 29 of th0 transistor 10 and the base-emitter voltage of the tran^
sistor 20. Also, the base-emitter voltage of the transistor 20 31 opposes the base^emitter voltage of the transistor 18. Since 32 the transistors 10 and 12 have their collector-emitter circuits ! ~~
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~ lU43~zo l , connected in series, .heir collector currents will be equ~l.
2 It can be appreciated that the collector currents of tlle tran-3 sistors 18 and 20 will also be equal. Accordin~ly, the summa-4 tion of the base-emitter voltages of all of the transistors will be proportional ~o the difference of their emitter areas.
6 Tl;at is, the difference of tl~c base-emitter voltages, ~Vbe, 7 w]lich is the voltage developed across one of the resistors 8 26-32 having a value other than zero, is dofined by the expres-9 sion:
~Vbe ~ Kq ln ~ tl) l2 where Jc is the combined current density of the transistors 13 12 and 18 and Jc is tlle combined current density of the tran-14 sistors 10 and 20. Accordingly, if the emitter areas of the transistors are of different values, the current density ratio 16¦ of the above expressiGn will be other than zero. It can be 17 Iappreciated, therelore, tha~ the voltage of an input source 181 which supplies a bias to each of the transistors 10, 12, 18 19 ¦and 20 will not affect the summation of the base-emitter volt-20 ¦ages, ~Vbe, developed on one of the resistors 26-32 which has -21 ¦a value other than zero. It can also be appreciated that this 22 ¦summation of the base-emitter voltages, ~Vbe, will be zero if `
23 lall of the emitter areas of the transistors aTe equal to one 24 ¦another.
25 ¦ An alternate embodiment of a four terminal network con-26 ¦structed in accordance with the principles of the present in-27 ¦vention is illustrated in Figure 2. As shown therein, tran-28 ¦sistors 34 and 36 are connected in series between a pair of 29 termina~s 42 and 44 and transistors 46 and 48 are connected in series between a pair of terminals S0 and 52. Resistors 54, 31 56, 58 and 60 are connected in the emitter circuits of the tran-32 sistors 34, 36, 46 and 48, respectively. It can be appreciated ,, ,, ., . ., J ~, ~ ' . -7 ~,,., . ,. ' ,........................... .,, , l- '' " .. ., " . . , . ," ., ; .. ... " ,. .. , , , " , ,." .. , , : , ,. .. ,. " " . , . , , ,, .. " ,, " ,. .. .. .... . ....
~ 1~)43420 11 from the drawings and the above description that the circuit 21 thus described in Figure 2 is similar to the circuit ill,ustrated 31 in Figure 1. A transistor 62 has its collector-emitter circuit 41 connected in series bet~Yeen tl~e terminal 50 and the collector 5¦ of the transistor 46 and has its base connected to the terminal 61 42. The transistor 62 isolates the collector of the transistor 7 ¦ 46 from any voltage changes whicll may occur on the ter~ninal 50 8 ¦ and raises the outpu; impedance of the circuit.
9 ¦ With reference to Figure 3, there'is shown a current
10 ¦regulator which is constructed in accordance with thc principles
11 ¦of the present invention. A voltage source, represented by
12 ¦V~ and V-, is connected to terminals 64 and 66. The circuit
13 ¦o Figure 3 is operative to provide a constant current through
14 la load (not shown) when it is connected across terminsls 68 and
15 170, regardless of variations in the supply voltage on the ter-
16 ¦minals 64 and 66.
17 ¦ The collector of a transis.or 72 is connected through a
18 ¦resistor 74 to the terminal 64 and 68, to its base, and to the
19 ¦base of a transistor 76 having its collector connected to the
20 ¦tcrminal 70. The collector- emitter circuit~of the transistor
21 172 is connected in series with the collector-emitter circuit of
22 la transistor 78 and the collector-emitter circuit of a transis- ,
23 tor 76 is connected in series with the co}lector-emitter cir-
24 cuit of a transistor 80. The junction between the transistors 72 and 78 is connected to the base of the transistor 80 and the 26 junction between the transistors 76 and 80 is connected to the 27 base of the transistor 78. The emitter of the transistor 78 28 is connected to the terminal 66 and the emitter of the transis-29 tor 80 is connected through a resistor 82 to the terminal 66.
The current regulator illustrated in Figure 3 is one 31 example of 8 practical embodiment of the circuit illustrated ' 3 in Figure 1. The only constraint on the circuit illustrated , ' : . . ,.
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1 in Figura 3 is that the resistor 74 must be of a value to pro-2 vide a current theretllrougl1 whicl~ is greater than the output 3 current of the transistor 72 divided by its beta. From inspec-4 tion of the circuit, it will be appreciated that the voltage d~veloped across the resistor 82 is equal to the sum of the 6 b~se-emitter voltages of the transistors 76 and 78 less the 7 sum of the base-emitter voltages of the transistors 72 and 80.
8 Since the s~mmation of the base-emitter voltages of tlle tran-9 sistors 72-80 is proportional to the dif~erence of their emitter areas, if any, the voltsge developed on the resistor 82 will 11 also be proportional to that summation. For example, if the 12 emitter areas of the tr~nsistors 72 and 78 are equal and, since 13 their collector currents are equal, tlleir base-emitter voltages -14 will cancel one another. In such an example, the voltage de-vcloped across the resistor 82 will equal to the base-emitter 16 voltage of the transistor 76 less the base-emitter voltage of -17 the transistor 80. This difference of the base-emitter voltages 18 is defined by the above expression where Jc and Jc are current 19 densities of the transistors 76 and 80, respectively. It can - -2~ be appreciated that the load current, ~hich is equal to the 21 current through the resistor 82, will remain constant since 22 its value depends upon the ratio of the current densities of 23 the transistors and such ratio will, of course, remain constant, 24 since the collector currents of the transistors having their collector-emitter circuits in series are equal to one another.
26 - With reference to Figure 4, there is shown a voltage 27 regulator circuit which employs the principles of the circuit 28 illustrated in Figure l. A curren; source, represented dia-29 ~rammatically by a dotted outline block which is designated with the reference numeral 84, includes a voltage source desig-31 nated by V~ and V- connected to terminals 86 and 88 and a re-32 sistor 90. It is to be understood, of course, that any current .. _,.. , . . , ' _g_ . -'.'''' ' l . . :.
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, ~ , , . . . , . ,: , 1~)43420 source may be employed for supplying the circuit. The circuit of Figure 4 supplies a regulated voltage across a pair of ter-minals 92 and 94.
Transistors 96, 98, 100 and 102 are connected in the same configuration as that of Figure 1. The collector of the transistor 96 is connected through a resistor 104 to one side of the suppl~ 84 and to the terminal 92. The emitter of the tran~istor 98 is connected through a resistor 106 to the ter~
minals 88 and 94.
The voltage developed across the resistor 106 is equal to the sum of the base-emitter voltages of the transistors 96 and 102 less the sum of the base-emitter voltages of the tran-Y, sistors 98 and 100. Since the voltage developed across the resistor 106 is independent of its resistance value, a low regulated voltage is developed thereon. This regulated voltage is reflected at the terminals 92 and 94 as an output voltage having a high degree of regulation. Furthermore, this voltage will be proportional to the difference of the emitter areas of the transistors and will be independent of the current supply 84 and the voltage supply on the terminals 86 and 88.
The circuit illustrated in Figure 4 performs such vol-tage regulation by controlling the current through the trans-i~tors 100 and 102 to maintain the voltage on the terminals 92 and 94 constant. The value of the voltage developed on the ter-minals 92 ~nd 94 is determined by!the difference of the emitter areas of the transistors. From inspection, it can be appreciated that the voltage across the terminals 92 and 94, Vs, is defined by the expression: -~
Vs ~Vbe ~ + Vbel + Vbe2 , ~2) , where~Vbe is the difference of the base-emitter voltages of the tran5istors having different emitter areas, R2 is the value ~0 .:
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.IJ J 104;~4Z0 I of the resistor 104, Rl is the value of the ~esistor 106, V~e 2 is the base-enlitter voltag~ of the transistor 96, and Vbc is 3 the base-cmitter voltage of the transistor 102. Since thc first 4 quantity in the above expression t2) has a positive temperature coefficient and the tl~o remaining quantities have a negative 6 temperature coefficient, at a particular output voltage on the 7 terminals 92 and 94, the circuit will e~hibit a zero termpera-8 ture coefficient. More particularly, SU5]l a zero temperature 9 coefficient occurs when the output voltage on the terminals 10 92 and 94 is equal to 2.4 volts or two times the extrapolated .
11 band gap of silicon.
12 When the supply current attempts to increase, the con-l3 duction level of the transistors 100 and 102 will increase, to 14 shunt current therethrough so that the voltage on the resistor 16 106 remains constant. By maintaining the voltage on the resis-l6 tor 106 constant, the voltage across the terminals 92 and 94 17 will also remain constant.
18 The circuit illustrated in Figure 5 is a buffer amplifier 19 which employs the prir.ciples of the circuit illustrated in Pigure 1. It can ~e appreciated from the drawing that the transistors 21 108, 110, 112 and 114 are connected together to form the circuit 22 illustrated in Figure 1 when all of the resistors 26-32 have a 23 value of zero. One side of a voltage supply, designated Vt, 24 is connected to the collector of the transistor 112 and through a resistor 116 to the collector of the transistor 108. The 2~ emitter of the transistor 114 is connected to one output ter-27 inal 118 and the emitter of the transistor 110 is connected 28 through an input si~nal source 120 to the other side of the 29 oltage supply, designated V-, and to another output terminal 30 122.
31 If the emitter areas of the transistors 108-114 are equal -32 to one another, the voltage of the input signal source 120 will ~
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16)434~0 be reflected exactly on the terminals 118 and 122. It can be appreciated that the input signal source 120 can be any source, including the circuit illustrated in Figure 4. The circuit of ~igure 5 presents a relatively high impedance to the input signal source 120 and provides a relatively low impedance output on the terminals 118 and 122. Furthermore, a relatively high ;
current output can be provided across the terminals 118 and 122 without a current limiting resistor in the circuit.
Since the limit of the circuit illustrated in Figure 5 is controlled by the betas of the transistors 108-114, the base drive to each of those transistors can be increased to permit a relatively high output current across the terminals 118 and 122. More particularly, a current amplifier 124 supplies a base drive to each of the transistors 108 and 112, a current amplifier 126 supplies a base drive to the transistor 114, and a current amplifier 128 supplies a base drive to the transistor ~ .
110. ~ccordingly, the base drive for all of the transistors i8 not derived from the voltage source designated V~ and V-, :: :
but i8 derived from the amplifiers 124, 126, and 128. Since the voltage gain of each of the amplifiers 124, 126 and 128 is - ~ -unity, the voltage developed across the terminals 118 and 122 will not be affected thereby.
It can be appreciated that the circuit illustrated in Figure 2 can also be employed as a current regulator, a voltage regulator and a buffer amplifier. Furthermore, the circuits illustrated in Figures 1 and 2 can be employed to provide a variety of input and output characteristics by controlling the -values of the resistors 26-32 and resistors 54-60. ~ ~
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The current regulator illustrated in Figure 3 is one 31 example of 8 practical embodiment of the circuit illustrated ' 3 in Figure 1. The only constraint on the circuit illustrated , ' : . . ,.
~ ~ -8-_ . . . . .-1:' ! ~ . . , ~, 1C)4342V
1 in Figura 3 is that the resistor 74 must be of a value to pro-2 vide a current theretllrougl1 whicl~ is greater than the output 3 current of the transistor 72 divided by its beta. From inspec-4 tion of the circuit, it will be appreciated that the voltage d~veloped across the resistor 82 is equal to the sum of the 6 b~se-emitter voltages of the transistors 76 and 78 less the 7 sum of the base-emitter voltages of the transistors 72 and 80.
8 Since the s~mmation of the base-emitter voltages of tlle tran-9 sistors 72-80 is proportional to the dif~erence of their emitter areas, if any, the voltsge developed on the resistor 82 will 11 also be proportional to that summation. For example, if the 12 emitter areas of the tr~nsistors 72 and 78 are equal and, since 13 their collector currents are equal, tlleir base-emitter voltages -14 will cancel one another. In such an example, the voltage de-vcloped across the resistor 82 will equal to the base-emitter 16 voltage of the transistor 76 less the base-emitter voltage of -17 the transistor 80. This difference of the base-emitter voltages 18 is defined by the above expression where Jc and Jc are current 19 densities of the transistors 76 and 80, respectively. It can - -2~ be appreciated that the load current, ~hich is equal to the 21 current through the resistor 82, will remain constant since 22 its value depends upon the ratio of the current densities of 23 the transistors and such ratio will, of course, remain constant, 24 since the collector currents of the transistors having their collector-emitter circuits in series are equal to one another.
26 - With reference to Figure 4, there is shown a voltage 27 regulator circuit which employs the principles of the circuit 28 illustrated in Figure l. A curren; source, represented dia-29 ~rammatically by a dotted outline block which is designated with the reference numeral 84, includes a voltage source desig-31 nated by V~ and V- connected to terminals 86 and 88 and a re-32 sistor 90. It is to be understood, of course, that any current .. _,.. , . . , ' _g_ . -'.'''' ' l . . :.
~.' . ., .~ . l, , . .
, ~ , , . . . , . ,: , 1~)43420 source may be employed for supplying the circuit. The circuit of Figure 4 supplies a regulated voltage across a pair of ter-minals 92 and 94.
Transistors 96, 98, 100 and 102 are connected in the same configuration as that of Figure 1. The collector of the transistor 96 is connected through a resistor 104 to one side of the suppl~ 84 and to the terminal 92. The emitter of the tran~istor 98 is connected through a resistor 106 to the ter~
minals 88 and 94.
The voltage developed across the resistor 106 is equal to the sum of the base-emitter voltages of the transistors 96 and 102 less the sum of the base-emitter voltages of the tran-Y, sistors 98 and 100. Since the voltage developed across the resistor 106 is independent of its resistance value, a low regulated voltage is developed thereon. This regulated voltage is reflected at the terminals 92 and 94 as an output voltage having a high degree of regulation. Furthermore, this voltage will be proportional to the difference of the emitter areas of the transistors and will be independent of the current supply 84 and the voltage supply on the terminals 86 and 88.
The circuit illustrated in Figure 4 performs such vol-tage regulation by controlling the current through the trans-i~tors 100 and 102 to maintain the voltage on the terminals 92 and 94 constant. The value of the voltage developed on the ter-minals 92 ~nd 94 is determined by!the difference of the emitter areas of the transistors. From inspection, it can be appreciated that the voltage across the terminals 92 and 94, Vs, is defined by the expression: -~
Vs ~Vbe ~ + Vbel + Vbe2 , ~2) , where~Vbe is the difference of the base-emitter voltages of the tran5istors having different emitter areas, R2 is the value ~0 .:
, ' , ', ~
Ph/~5 ' .,, , . . ,,"., , ,`' , .' ',, . ~
.IJ J 104;~4Z0 I of the resistor 104, Rl is the value of the ~esistor 106, V~e 2 is the base-enlitter voltag~ of the transistor 96, and Vbc is 3 the base-cmitter voltage of the transistor 102. Since thc first 4 quantity in the above expression t2) has a positive temperature coefficient and the tl~o remaining quantities have a negative 6 temperature coefficient, at a particular output voltage on the 7 terminals 92 and 94, the circuit will e~hibit a zero termpera-8 ture coefficient. More particularly, SU5]l a zero temperature 9 coefficient occurs when the output voltage on the terminals 10 92 and 94 is equal to 2.4 volts or two times the extrapolated .
11 band gap of silicon.
12 When the supply current attempts to increase, the con-l3 duction level of the transistors 100 and 102 will increase, to 14 shunt current therethrough so that the voltage on the resistor 16 106 remains constant. By maintaining the voltage on the resis-l6 tor 106 constant, the voltage across the terminals 92 and 94 17 will also remain constant.
18 The circuit illustrated in Figure 5 is a buffer amplifier 19 which employs the prir.ciples of the circuit illustrated in Pigure 1. It can ~e appreciated from the drawing that the transistors 21 108, 110, 112 and 114 are connected together to form the circuit 22 illustrated in Figure 1 when all of the resistors 26-32 have a 23 value of zero. One side of a voltage supply, designated Vt, 24 is connected to the collector of the transistor 112 and through a resistor 116 to the collector of the transistor 108. The 2~ emitter of the transistor 114 is connected to one output ter-27 inal 118 and the emitter of the transistor 110 is connected 28 through an input si~nal source 120 to the other side of the 29 oltage supply, designated V-, and to another output terminal 30 122.
31 If the emitter areas of the transistors 108-114 are equal -32 to one another, the voltage of the input signal source 120 will ~
~ r .
" ~ .
r~
J
16)434~0 be reflected exactly on the terminals 118 and 122. It can be appreciated that the input signal source 120 can be any source, including the circuit illustrated in Figure 4. The circuit of ~igure 5 presents a relatively high impedance to the input signal source 120 and provides a relatively low impedance output on the terminals 118 and 122. Furthermore, a relatively high ;
current output can be provided across the terminals 118 and 122 without a current limiting resistor in the circuit.
Since the limit of the circuit illustrated in Figure 5 is controlled by the betas of the transistors 108-114, the base drive to each of those transistors can be increased to permit a relatively high output current across the terminals 118 and 122. More particularly, a current amplifier 124 supplies a base drive to each of the transistors 108 and 112, a current amplifier 126 supplies a base drive to the transistor 114, and a current amplifier 128 supplies a base drive to the transistor ~ .
110. ~ccordingly, the base drive for all of the transistors i8 not derived from the voltage source designated V~ and V-, :: :
but i8 derived from the amplifiers 124, 126, and 128. Since the voltage gain of each of the amplifiers 124, 126 and 128 is - ~ -unity, the voltage developed across the terminals 118 and 122 will not be affected thereby.
It can be appreciated that the circuit illustrated in Figure 2 can also be employed as a current regulator, a voltage regulator and a buffer amplifier. Furthermore, the circuits illustrated in Figures 1 and 2 can be employed to provide a variety of input and output characteristics by controlling the -values of the resistors 26-32 and resistors 54-60. ~ ~
: - ' ~ 2 -:
. ~ . . . . . .. .
, , , , , , , ~; .- . ; ~ ~ ,
Claims (16)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A circuit disposed for connection to an input sup-ply for providing an output which is independent of that supply, comprising a plurality of transistors, and means responsive to the input supply for generating a base-emitter voltage on all of said transistors, the base-emitter junctions of said transistors being connected serially in a loop with one another, such that the summation of the base-emitter voltages of said transis-tors is developed as an output voltage between the base-emitter junctions of two adjacent ones of said transistors in said loop, said plurality of transistors including a first pair of transistors having their collector-emitter circuits con-nected in series and a second pair of transistors having their collector-emitter circuits connected in series, the collector currents of any of said transistors having their collector-emitter circuits connected in series being equal to one another and their base-emitter voltages opposing one another around said loop, such that said summation of the base-emitter voltages is independent of the collector currents of said transistors and only proportional to the dif-ference of the emitter areas of said transistors.
2. The circuit of claim 1, wherein the emitter areas of at least two of said transistors are different from one an-other.
3. The circuit of claim 2, wherein said output voltage is proportional to the difference of the emitter areas of said transistors.
4. The circuit of claim 3, further comprising a re-sistor connected between the base-emitter junctions of said two adjacent transistors, such that said output voltage is developed on said resistor, and wherein the current through said resistor is available at the collector of one of said transistors as an output.
5. The circuit of claim 3, further comprising a resis-tor connected between the base-emitter junctions of said two adjacent transistors, such that said output voltage is developed on said resistor, and wherein the current through one of said transistors is proportional to the value of said resistor.
6. The circuit of claim 1, wherein said generating means includes a first connection from the junction between said first pair of transistors to the base of a first one of said second pair of transistors, a second connection from the junction between said second pair of transistors to the base of a first one of said first pair of transistors, and a third connection between the base of a second one of said first pair of transistors to the base of a second one of said second pair of transistors.
7. The circuit of claim 6, wherein said generating means further includes a fourth connection from the collector of one of said second transistors to its base.
8. The circuit of claim 7, wherein said generating means further includes a plurality of current amplifiers, one in each of said first, second and third connections.
9. The circuit of claim 8, wherein the collectors of said second transistors are disposed for connection to one side of the input supply and the emitter of one of said first tran-sistors is disposed for connection through an input voltage source to the other side of the input supply.
10. A four terminal network, comprising (a) a first pair of transistors having their collector-emitter circuits connected in series between a first pair of terminals, (b) a second pair of transistors having their collector-emitter circuits connected in series between a second pair of terminals, (c) a connection from one of the first pair of terminals to the base of a first one of said first pair of transistors and to the base of a first one of said second pair of tran-sistors, (d) a connection from the junction of said first pair of transistors to the base of a second one of said second pair of transistors, and (e) a connection from the junction of said second pair of transistors to the base of a second one of said first pair of transistors.
11. The network of claim 10, further comprising a resis-tor connected in the emitter circuit of one of said transistors.
12. The network of claim 11, wherein said resistor is connected between said first pair of transistors.
13. The network of claim 11, wherein said resistor is connected between said second pair of transistors.
14. The network of claim 11, wherein said resistor is connected between the emitter of said second one of said first pair of transistors to a second one of the first pair of ter-minals.
15. The network of claim 11, wherein said resistor is connected between the emitter of said second one of said second pair of transistors to one of the second pair of terminals.
16. The network of claim 10, further comprising an amplifier in each of said connections.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US521363A US3930172A (en) | 1974-11-06 | 1974-11-06 | Input supply independent circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1043420A true CA1043420A (en) | 1978-11-28 |
Family
ID=24076456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA232,980A Expired CA1043420A (en) | 1974-11-06 | 1975-08-06 | Input supply independent circuit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3930172A (en) |
| JP (1) | JPS5839412B2 (en) |
| CA (1) | CA1043420A (en) |
| DE (1) | DE2549575C2 (en) |
| FR (1) | FR2290784A1 (en) |
| GB (2) | GB1516126A (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1506881A (en) * | 1975-02-24 | 1978-04-12 | Rca Corp | Current divider |
| US4177417A (en) * | 1978-03-02 | 1979-12-04 | Motorola, Inc. | Reference circuit for providing a plurality of regulated currents having desired temperature characteristics |
| US4268759A (en) * | 1979-05-21 | 1981-05-19 | Analog Devices, Incorporated | Signal-processing circuitry with intrinsic temperature insensitivity |
| JPS6058601B2 (en) * | 1980-04-14 | 1985-12-20 | 株式会社東芝 | conversion circuit |
| US4389619A (en) * | 1981-02-02 | 1983-06-21 | Rca Corporation | Adjustable-gain current amplifier for temperature-independent trimming |
| US4366444A (en) * | 1981-02-02 | 1982-12-28 | Rca Corporation | Temperature-independent current trimming arrangement |
| JPS57160206A (en) * | 1981-03-27 | 1982-10-02 | Toshiba Corp | Fine current source circuit |
| JPS57201877U (en) * | 1981-06-17 | 1982-12-22 | ||
| JPH0614302B2 (en) * | 1981-08-20 | 1994-02-23 | 株式会社東芝 | Transistor circuit |
| US4479086A (en) * | 1981-09-24 | 1984-10-23 | Tokyo Shibaura Denki Kabushiki Kaisha | Transistor circuit |
| NL8200974A (en) * | 1982-03-10 | 1983-10-03 | Philips Nv | POWER DISCRIMINATION CIRCUIT. |
| US4540900A (en) * | 1982-07-01 | 1985-09-10 | Burr-Brown Corporation | Reduced swing latch circuit utilizing gate current proportional to temperature |
| US4461991A (en) * | 1983-02-28 | 1984-07-24 | Motorola, Inc. | Current source circuit having reduced error |
| US4766367A (en) * | 1987-07-20 | 1988-08-23 | Comlinear Corporation | Current mirror with unity gain buffer |
| US4816742A (en) * | 1988-02-16 | 1989-03-28 | North American Philips Corporation, Signetics Division | Stabilized current and voltage reference sources |
| US4837496A (en) * | 1988-03-28 | 1989-06-06 | Linear Technology Corporation | Low voltage current source/start-up circuit |
| DE3936392A1 (en) * | 1989-11-02 | 1991-05-08 | Telefunken Electronic Gmbh | Current stabilising circuit e.g. for amplifiers - has two transistor emitters coupled to reference point, and first transistor base linked to second transistor collector |
| JP2755848B2 (en) * | 1990-11-16 | 1998-05-25 | 株式会社東芝 | Micro voltage detection circuit and current limiting circuit using the same |
| US5134358A (en) * | 1991-01-31 | 1992-07-28 | Texas Instruments Incorporated | Improved current mirror for sensing current |
| FR2718259A1 (en) * | 1994-03-30 | 1995-10-06 | Philips Composants | Regulator circuit providing a voltage independent of the power supply and the temperature. |
| DE19504289C1 (en) * | 1995-02-09 | 1996-03-28 | Siemens Ag | Integrated current source circuit |
| JP2874634B2 (en) * | 1996-03-01 | 1999-03-24 | 日本電気株式会社 | Reference voltage circuit |
| DE19821906C1 (en) * | 1998-05-15 | 2000-03-02 | Siemens Ag | Clamping circuit |
| US6404223B1 (en) | 2001-01-22 | 2002-06-11 | Mayo Foundation For Medical Education And Research | Self-terminating current mirror transceiver logic |
| GB2355552A (en) | 1999-10-20 | 2001-04-25 | Ericsson Telefon Ab L M | Electronic circuit for supplying a reference current |
| US6232829B1 (en) | 1999-11-18 | 2001-05-15 | National Semiconductor Corporation | Bandgap voltage reference circuit with an increased difference voltage |
| EP2329230A1 (en) * | 2008-08-28 | 2011-06-08 | Adaptalog Limited | Temperature sensitive circuit |
| US9285820B2 (en) | 2012-02-03 | 2016-03-15 | Analog Devices, Inc. | Ultra-low noise voltage reference circuit |
| EP3929694B1 (en) | 2020-06-22 | 2023-08-30 | NXP USA, Inc. | A voltage regulator |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1600781A (en) * | 1968-03-15 | 1970-07-27 | ||
| US3629692A (en) * | 1971-01-11 | 1971-12-21 | Rca Corp | Current source with positive feedback current repeater |
| US3842412A (en) * | 1972-11-22 | 1974-10-15 | Analog Devices Inc | High resolution monolithic digital-to-analog converter |
-
1974
- 1974-11-06 US US521363A patent/US3930172A/en not_active Expired - Lifetime
-
1975
- 1975-07-28 GB GB918/78A patent/GB1516126A/en not_active Expired
- 1975-07-28 GB GB31469/75A patent/GB1516125A/en not_active Expired
- 1975-08-06 CA CA232,980A patent/CA1043420A/en not_active Expired
- 1975-10-09 JP JP50122369A patent/JPS5839412B2/en not_active Expired
- 1975-11-04 FR FR7533617A patent/FR2290784A1/en active Granted
- 1975-11-05 DE DE2549575A patent/DE2549575C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3930172A (en) | 1975-12-30 |
| JPS5165858A (en) | 1976-06-07 |
| FR2290784B1 (en) | 1980-02-15 |
| JPS5839412B2 (en) | 1983-08-30 |
| DE2549575A1 (en) | 1976-05-13 |
| DE2549575C2 (en) | 1986-12-11 |
| GB1516125A (en) | 1978-06-28 |
| GB1516126A (en) | 1978-06-28 |
| FR2290784A1 (en) | 1976-06-04 |
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