BR9610285A - Aparelho para realização de operações de multiplicação e adição em dados compactados - Google Patents

Aparelho para realização de operações de multiplicação e adição em dados compactados

Info

Publication number
BR9610285A
BR9610285A BR9610285A BR9610285A BR9610285A BR 9610285 A BR9610285 A BR 9610285A BR 9610285 A BR9610285 A BR 9610285A BR 9610285 A BR9610285 A BR 9610285A BR 9610285 A BR9610285 A BR 9610285A
Authority
BR
Brazil
Prior art keywords
compressed data
addition operations
performing multiplication
multiplication
operations
Prior art date
Application number
BR9610285A
Other languages
English (en)
Portuguese (pt)
Inventor
Ahmet Bindal
Derrick Chu Lin
Wolf Witt
Tuan H Bui
Eiichi Kowashi
Stephen A Fisher
Carole Dulong
Larry M Mennemeier
Millind Mittal
Alexander D Peleg
Benny Eitan
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/522,067 external-priority patent/US6385634B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9610285A publication Critical patent/BR9610285A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7857—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Computer Hardware Design (AREA)
  • Discrete Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Hair Curling (AREA)
  • Holo Graphy (AREA)
BR9610285A 1995-08-31 1996-08-07 Aparelho para realização de operações de multiplicação e adição em dados compactados BR9610285A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/522,067 US6385634B1 (en) 1995-08-31 1995-08-31 Method for performing multiply-add operations on packed data
US08/606,212 US6035316A (en) 1995-08-31 1996-02-23 Apparatus for performing multiply-add operations on packed data
PCT/US1996/012799 WO1997008610A1 (en) 1995-08-31 1996-08-07 An apparatus for performing multiply-add operations on packed data

Publications (1)

Publication Number Publication Date
BR9610285A true BR9610285A (pt) 1999-03-16

Family

ID=27060694

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9610285A BR9610285A (pt) 1995-08-31 1996-08-07 Aparelho para realização de operações de multiplicação e adição em dados compactados

Country Status (14)

Country Link
EP (1) EP0847552B1 (enExample)
JP (2) JP3750820B2 (enExample)
CN (2) CN100465874C (enExample)
AU (1) AU717246B2 (enExample)
BR (1) BR9610285A (enExample)
CA (1) CA2230108C (enExample)
DE (1) DE69624578T2 (enExample)
HU (1) HUP9900030A3 (enExample)
IL (1) IL123241A (enExample)
MX (1) MX9801571A (enExample)
NO (1) NO317739B1 (enExample)
PL (1) PL325231A1 (enExample)
RU (1) RU2139564C1 (enExample)
WO (1) WO1997008610A1 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667635B2 (ja) 1998-01-21 2005-07-06 松下電器産業株式会社 演算装置
US7392275B2 (en) 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
EP2267596B1 (en) * 1999-05-12 2018-08-15 Analog Devices, Inc. Processor core for processing instructions of different formats
US6571265B1 (en) * 1999-10-29 2003-05-27 Intel Corporation Mechanism to detect IEEE underflow exceptions on speculative floating-point operations
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US7430578B2 (en) 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
JP4136432B2 (ja) * 2002-04-15 2008-08-20 松下電器産業株式会社 図形描画装置
CN1310130C (zh) * 2003-03-12 2007-04-11 中国科学院声学研究所 一种乘法器的重构运算方法及可重构乘法器
US7424501B2 (en) 2003-06-30 2008-09-09 Intel Corporation Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations
US7539714B2 (en) * 2003-06-30 2009-05-26 Intel Corporation Method, apparatus, and instruction for performing a sign operation that multiplies
US7689641B2 (en) * 2003-06-30 2010-03-30 Intel Corporation SIMD integer multiply high with round and shift
US7873815B2 (en) * 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7995845B2 (en) * 2008-01-30 2011-08-09 Qualcomm Incorporated Digital signal pattern detection and classification using kernel fusion
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8103858B2 (en) * 2008-06-30 2012-01-24 Intel Corporation Efficient parallel floating point exception handling in a processor
US8239442B2 (en) * 2008-08-08 2012-08-07 Analog Devices, Inc. Computing module for efficient FFT and FIR hardware accelerator
CN101706712B (zh) * 2009-11-27 2011-08-31 北京龙芯中科技术服务中心有限公司 浮点向量乘加运算装置和方法
CN102541814B (zh) * 2010-12-27 2015-10-14 北京国睿中数科技股份有限公司 用于数据通信处理器的矩阵计算装置和方法
US8909687B2 (en) * 2012-01-19 2014-12-09 Mediatek Singapore Pte. Ltd. Efficient FIR filters
DE102013209657A1 (de) * 2013-05-24 2014-11-27 Robert Bosch Gmbh FMA-Einheit, insbesondere zur Verwendung in einer Modellberechnungseinheit zur rein hardwarebasierten Berechnung von Funktionsmodellen
CN103677739B (zh) * 2013-11-28 2016-08-17 中国航天科技集团公司第九研究院第七七一研究所 一种可配置的乘累加运算单元及其构成的乘累加运算阵列
WO2015147895A1 (en) * 2014-03-26 2015-10-01 Intel Corporation Three source operand floating point addition processors, methods, systems, and instructions
RU2562411C1 (ru) * 2014-12-10 2015-09-10 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кубанский государственный технологический университет" (ФГБОУ ВПО "КубГТУ") Устройство для вычисления модуля комплексного числа
US10049082B2 (en) * 2016-09-15 2018-08-14 Altera Corporation Dot product based processing elements
RU2653310C1 (ru) * 2017-05-24 2018-05-07 федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") Устройство для умножения числа по модулю на константу
US10705839B2 (en) * 2017-12-21 2020-07-07 Intel Corporation Apparatus and method for multiplying, summing, and accumulating sets of packed bytes
CN109117114B (zh) * 2018-08-16 2023-06-02 电子科技大学 一种基于查找表的低复杂度近似乘法器
US12164882B2 (en) * 2020-07-14 2024-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. In-memory computation circuit and method
CN113010146B (zh) * 2021-03-05 2022-02-11 唐山恒鼎科技有限公司 一种混合信号乘法器
CN113076083B (zh) * 2021-06-04 2021-08-31 南京后摩智能科技有限公司 数据乘加运算电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575812A (en) * 1984-05-31 1986-03-11 Motorola, Inc. X×Y Bit array multiplier/accumulator circuit
CN85107063A (zh) * 1985-09-27 1987-01-31 耿树贵 整数多功能叠接单元的阵列乘法器
JPS6297060A (ja) * 1985-10-23 1987-05-06 Mitsubishi Electric Corp デイジタルシグナルプロセツサ
JPS6297033A (ja) * 1985-10-24 1987-05-06 Hitachi Ltd 乗算装置
US4769780A (en) * 1986-02-10 1988-09-06 International Business Machines Corporation High speed multiplier
US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
RU2012039C1 (ru) * 1988-12-06 1994-04-30 Пензенский научно-исследовательский электротехнический институт Однотактный умножитель двоичных чисел
CA1311063C (en) * 1988-12-16 1992-12-01 Tokumichi Murakami Digital signal processor
US5047973A (en) * 1989-04-26 1991-09-10 Texas Instruments Incorporated High speed numerical processor for performing a plurality of numeric functions
RU2021633C1 (ru) * 1991-07-10 1994-10-15 Научно-исследовательский институт электронных вычислительных машин Устройство для умножения чисел
RU2022339C1 (ru) * 1992-01-31 1994-10-30 Винницкий политехнический институт Множительное устройство
JP3210420B2 (ja) * 1992-06-25 2001-09-17 キヤノン株式会社 整数上の乗算回路

Also Published As

Publication number Publication date
DE69624578T2 (de) 2003-09-04
EP0847552B1 (en) 2002-10-30
RU2139564C1 (ru) 1999-10-10
CN1107905C (zh) 2003-05-07
JPH11511577A (ja) 1999-10-05
HUP9900030A2 (hu) 1999-04-28
CN100465874C (zh) 2009-03-04
JP4064989B2 (ja) 2008-03-19
NO980873L (no) 1998-04-28
AU717246B2 (en) 2000-03-23
IL123241A0 (en) 1998-09-24
DE69624578D1 (de) 2002-12-05
CN1549106A (zh) 2004-11-24
IL123241A (en) 2001-10-31
AU6951196A (en) 1997-03-19
NO980873D0 (no) 1998-02-27
CA2230108C (en) 2000-12-12
NO317739B1 (no) 2004-12-13
HUP9900030A3 (en) 1999-11-29
MX9801571A (es) 1998-05-31
EP0847552A4 (en) 2000-01-12
PL325231A1 (en) 1998-07-06
CN1200821A (zh) 1998-12-02
CA2230108A1 (en) 1997-03-06
EP0847552A1 (en) 1998-06-17
HK1012513A1 (en) 1999-08-06
JP3750820B2 (ja) 2006-03-01
WO1997008610A1 (en) 1997-03-06
JP2006107463A (ja) 2006-04-20

Similar Documents

Publication Publication Date Title
DE69732943D1 (de) Datenverarbeitungsvorrichtung und -verfahren
BR9710877A (pt) Aparelho para processamento de dados girados e intercalados
DE69730645D1 (de) Datenverarbeitungsverfahren und -gerät
KR970700962A (ko) 멀티유저-간섭 감소 장치 및 방법과 코드분할 다중 액세스 통신 시스템(method and apparatus for multiuser-interference reduction)
DE69530128D1 (de) Sicherheit für rechnerbetriebsmittel
DE69827544D1 (de) Datenverarbeitungsgerät und -Verfahren
DE69724397D1 (de) Informationsverarbeitungsgerät und -verfahren
DE69820143D1 (de) Datenverarbeitungsgerät und -verfahren
HUP9900030A3 (en) An apparatus for performing multiply-add operations on packed data
DE69739432D1 (de) Informationsverarbeitungsgerät und -verfahren
DE69712725D1 (de) Informationsverarbeitungsgerät und -verfahren
KR950702050A (ko) 자료 세트 비교장치 및 그 방법(method and apparatus for comparing data sets)
DE69510251D1 (de) Informationsverarbeitungsverfahren und -vorrichtung
DE69630784D1 (de) Datenverarbeitungsgerät und -verfahren
DE69623284D1 (de) Datenverarbeitungsgerät und -verfahren
BR9608705A (pt) Método e aparelho para retirar amostra
DE69525489D1 (de) Informationsverarbeitungsgerät
DE69724374D1 (de) Informationsverarbeitungsgerät
DE69617677D1 (de) Datenverarbeitungsgerät und -verfahren
DE69732061D1 (de) Datenverarbeitungssystem und -verfahren
KR960011743A (ko) 데이타 처리 시스템에 관한 장치 및 방법
DE69517870D1 (de) Datenverarbeitungsvorrichtung
DE69534415D1 (de) Informationsverarbeitungsgerät
ID18976A (id) Metode dan unit pemrosesan data untuk kromatografy
NO974806D0 (no) Fremgangsmåte og system for analysering av data

Legal Events

Date Code Title Description
EG Technical examination (opinion): publication of technical examination (opinion)
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 07/08/1996, OBSERVADAS AS CONDICOES LEGAIS.

B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 07/08/2016