HUP9900030A2 - Berendezés szorzási-összeadási műveletek végrehajtására tömörített adatokon - Google Patents
Berendezés szorzási-összeadási műveletek végrehajtására tömörített adatokonInfo
- Publication number
- HUP9900030A2 HUP9900030A2 HU9900030A HUP9900030A HUP9900030A2 HU P9900030 A2 HUP9900030 A2 HU P9900030A2 HU 9900030 A HU9900030 A HU 9900030A HU P9900030 A HUP9900030 A HU P9900030A HU P9900030 A2 HUP9900030 A2 HU P9900030A2
- Authority
- HU
- Hungary
- Prior art keywords
- adder
- hair
- comb
- coupled
- packed data
- Prior art date
Links
- 230000009194 climbing Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
- G06F15/7857—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
- G06F7/4812—Complex multiplication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Computer Hardware Design (AREA)
- Algebra (AREA)
- Discrete Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
- Electrophonic Musical Instruments (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Controls And Circuits For Display Device (AREA)
- Holo Graphy (AREA)
- Hair Curling (AREA)
Abstract
Egy prőcesszőr egy első és egy másődik tárral rendelkezik, amelybenegy első, ill. másődik tömörített adat van elhelyezve. Mindegyiktömörített adat egy első, másődik, harmadik és negyedik adatelemettartalmaz. Egy szőrzó-összeadó áramkör van az első és a másődiktárterülethez kapcsőlva. A szőrzó-összeadó áramkör egy első, másődik,harmadik és negyedik szőrzót (810-813) tartalmaz, ahől mindegyikszőrzó (810-813) bemeneteire az említett adatelemek egy megfelelőhalmaza kerül. A szőrzó-összeadó áramkör ezen kívül tartalmaz egy elsőösszeadót (850), amely az első és másődik szőrzóhőz (810, 811) vankapcsőlva, és egy másődik összeadót (851), amely a harmadik ésnegyedik szőrzóhőz (812, 813) van kapcsőlva. Egy harmadik tárterület(871) az összeadókhőz (850, 851) van kapcsőlva. a harmadik tárterület(871) egy első és egy másődik mezőt tartalmaz, amelyek az első, ill.másődik összeadó (850, 851) kimenetét egy harmadik tömörített adatelső és másődik adatelemként tárőlják. ŕ
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/522,067 US6385634B1 (en) | 1995-08-31 | 1995-08-31 | Method for performing multiply-add operations on packed data |
US08/606,212 US6035316A (en) | 1995-08-31 | 1996-02-23 | Apparatus for performing multiply-add operations on packed data |
Publications (2)
Publication Number | Publication Date |
---|---|
HUP9900030A2 true HUP9900030A2 (hu) | 1999-04-28 |
HUP9900030A3 HUP9900030A3 (en) | 1999-11-29 |
Family
ID=27060694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HU9900030A HUP9900030A3 (en) | 1995-08-31 | 1996-08-07 | An apparatus for performing multiply-add operations on packed data |
Country Status (15)
Country | Link |
---|---|
EP (1) | EP0847552B1 (hu) |
JP (2) | JP3750820B2 (hu) |
CN (2) | CN1107905C (hu) |
AU (1) | AU717246B2 (hu) |
BR (1) | BR9610285A (hu) |
CA (1) | CA2230108C (hu) |
DE (1) | DE69624578T2 (hu) |
HK (1) | HK1012513A1 (hu) |
HU (1) | HUP9900030A3 (hu) |
IL (1) | IL123241A (hu) |
MX (1) | MX9801571A (hu) |
NO (1) | NO317739B1 (hu) |
PL (1) | PL325231A1 (hu) |
RU (1) | RU2139564C1 (hu) |
WO (1) | WO1997008610A1 (hu) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999038088A1 (fr) | 1998-01-21 | 1999-07-29 | Matsushita Electric Industrial Co., Ltd. | Procede et dispositif pour operation arithmetique |
US7392275B2 (en) | 1998-03-31 | 2008-06-24 | Intel Corporation | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |
US7395302B2 (en) | 1998-03-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing horizontal addition and subtraction |
EP2267896A3 (en) * | 1999-05-12 | 2013-02-20 | Analog Devices, Inc. | Method for implementing finite impulse response filters |
JP4136432B2 (ja) * | 2002-04-15 | 2008-08-20 | 松下電器産業株式会社 | 図形描画装置 |
CN1310130C (zh) * | 2003-03-12 | 2007-04-11 | 中国科学院声学研究所 | 一种乘法器的重构运算方法及可重构乘法器 |
US7424501B2 (en) | 2003-06-30 | 2008-09-09 | Intel Corporation | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations |
US7930336B2 (en) | 2006-12-05 | 2011-04-19 | Altera Corporation | Large multiplier for programmable logic device |
US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
US7995845B2 (en) * | 2008-01-30 | 2011-08-09 | Qualcomm Incorporated | Digital signal pattern detection and classification using kernel fusion |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8103858B2 (en) * | 2008-06-30 | 2012-01-24 | Intel Corporation | Efficient parallel floating point exception handling in a processor |
US8239442B2 (en) * | 2008-08-08 | 2012-08-07 | Analog Devices, Inc. | Computing module for efficient FFT and FIR hardware accelerator |
CN101706712B (zh) * | 2009-11-27 | 2011-08-31 | 北京龙芯中科技术服务中心有限公司 | 浮点向量乘加运算装置和方法 |
CN102541814B (zh) * | 2010-12-27 | 2015-10-14 | 北京国睿中数科技股份有限公司 | 用于数据通信处理器的矩阵计算装置和方法 |
US8909687B2 (en) * | 2012-01-19 | 2014-12-09 | Mediatek Singapore Pte. Ltd. | Efficient FIR filters |
DE102013209657A1 (de) * | 2013-05-24 | 2014-11-27 | Robert Bosch Gmbh | FMA-Einheit, insbesondere zur Verwendung in einer Modellberechnungseinheit zur rein hardwarebasierten Berechnung von Funktionsmodellen |
CN103677739B (zh) * | 2013-11-28 | 2016-08-17 | 中国航天科技集团公司第九研究院第七七一研究所 | 一种可配置的乘累加运算单元及其构成的乘累加运算阵列 |
KR101893814B1 (ko) * | 2014-03-26 | 2018-10-04 | 인텔 코포레이션 | 3 소스 피연산자 부동 소수점 가산 프로세서, 방법, 시스템, 및 명령어 |
RU2562411C1 (ru) * | 2014-12-10 | 2015-09-10 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кубанский государственный технологический университет" (ФГБОУ ВПО "КубГТУ") | Устройство для вычисления модуля комплексного числа |
US10049082B2 (en) * | 2016-09-15 | 2018-08-14 | Altera Corporation | Dot product based processing elements |
RU2653310C1 (ru) * | 2017-05-24 | 2018-05-07 | федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") | Устройство для умножения числа по модулю на константу |
CN109117114B (zh) * | 2018-08-16 | 2023-06-02 | 电子科技大学 | 一种基于查找表的低复杂度近似乘法器 |
US20220019407A1 (en) * | 2020-07-14 | 2022-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-memory computation circuit and method |
CN113010146B (zh) * | 2021-03-05 | 2022-02-11 | 唐山恒鼎科技有限公司 | 一种混合信号乘法器 |
CN113076083B (zh) * | 2021-06-04 | 2021-08-31 | 南京后摩智能科技有限公司 | 数据乘加运算电路 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN85107063A (zh) * | 1985-09-27 | 1987-01-31 | 耿树贵 | 整数多功能叠接单元的阵列乘法器 |
JPS6297060A (ja) * | 1985-10-23 | 1987-05-06 | Mitsubishi Electric Corp | デイジタルシグナルプロセツサ |
US4985848A (en) * | 1987-09-14 | 1991-01-15 | Visual Information Technologies, Inc. | High speed image processing system using separate data processor and address generator |
CA1311063C (en) * | 1988-12-16 | 1992-12-01 | Tokumichi Murakami | Digital signal processor |
US5047973A (en) * | 1989-04-26 | 1991-09-10 | Texas Instruments Incorporated | High speed numerical processor for performing a plurality of numeric functions |
JP3210420B2 (ja) * | 1992-06-25 | 2001-09-17 | キヤノン株式会社 | 整数上の乗算回路 |
-
1996
- 1996-08-07 HU HU9900030A patent/HUP9900030A3/hu unknown
- 1996-08-07 MX MX9801571A patent/MX9801571A/es unknown
- 1996-08-07 BR BR9610285A patent/BR9610285A/pt not_active IP Right Cessation
- 1996-08-07 IL IL12324196A patent/IL123241A/en not_active IP Right Cessation
- 1996-08-07 CN CN96197836A patent/CN1107905C/zh not_active Expired - Lifetime
- 1996-08-07 DE DE69624578T patent/DE69624578T2/de not_active Expired - Lifetime
- 1996-08-07 PL PL96325231A patent/PL325231A1/xx unknown
- 1996-08-07 JP JP51029097A patent/JP3750820B2/ja not_active Expired - Lifetime
- 1996-08-07 EP EP96930495A patent/EP0847552B1/en not_active Expired - Lifetime
- 1996-08-07 WO PCT/US1996/012799 patent/WO1997008610A1/en active IP Right Grant
- 1996-08-07 RU RU98105621A patent/RU2139564C1/ru active
- 1996-08-07 AU AU69511/96A patent/AU717246B2/en not_active Ceased
- 1996-08-07 CA CA002230108A patent/CA2230108C/en not_active Expired - Fee Related
- 1996-08-07 CN CNB031202993A patent/CN100465874C/zh not_active Expired - Lifetime
-
1998
- 1998-02-27 NO NO19980873A patent/NO317739B1/no not_active IP Right Cessation
- 1998-12-17 HK HK98113897A patent/HK1012513A1/xx not_active IP Right Cessation
-
2005
- 2005-08-29 JP JP2005248479A patent/JP4064989B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0847552A1 (en) | 1998-06-17 |
PL325231A1 (en) | 1998-07-06 |
AU717246B2 (en) | 2000-03-23 |
AU6951196A (en) | 1997-03-19 |
CA2230108A1 (en) | 1997-03-06 |
CN1549106A (zh) | 2004-11-24 |
IL123241A (en) | 2001-10-31 |
JP3750820B2 (ja) | 2006-03-01 |
DE69624578D1 (de) | 2002-12-05 |
JPH11511577A (ja) | 1999-10-05 |
JP2006107463A (ja) | 2006-04-20 |
IL123241A0 (en) | 1998-09-24 |
WO1997008610A1 (en) | 1997-03-06 |
CN1107905C (zh) | 2003-05-07 |
DE69624578T2 (de) | 2003-09-04 |
CA2230108C (en) | 2000-12-12 |
NO980873L (no) | 1998-04-28 |
NO980873D0 (no) | 1998-02-27 |
RU2139564C1 (ru) | 1999-10-10 |
CN1200821A (zh) | 1998-12-02 |
BR9610285A (pt) | 1999-03-16 |
HUP9900030A3 (en) | 1999-11-29 |
EP0847552B1 (en) | 2002-10-30 |
JP4064989B2 (ja) | 2008-03-19 |
MX9801571A (es) | 1998-05-31 |
HK1012513A1 (en) | 1999-08-06 |
EP0847552A4 (en) | 2000-01-12 |
NO317739B1 (no) | 2004-12-13 |
CN100465874C (zh) | 2009-03-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD9A | Lapse of provisional protection due to non-payment of fees |