BR9406096A - Elemento de retardo diferencial linha de retardo diferencial alinhador de fase sincronizador de bits e controle de função para o mesmo e gerador de referência auto-adaptável - Google Patents

Elemento de retardo diferencial linha de retardo diferencial alinhador de fase sincronizador de bits e controle de função para o mesmo e gerador de referência auto-adaptável

Info

Publication number
BR9406096A
BR9406096A BR9406096A BR9406096A BR9406096A BR 9406096 A BR9406096 A BR 9406096A BR 9406096 A BR9406096 A BR 9406096A BR 9406096 A BR9406096 A BR 9406096A BR 9406096 A BR9406096 A BR 9406096A
Authority
BR
Brazil
Prior art keywords
differential delay
self
function control
reference generator
line phase
Prior art date
Application number
BR9406096A
Other languages
English (en)
Inventor
Tord Lennart Haulin
Per M Segerback
Heinz Mader
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9406096A publication Critical patent/BR9406096A/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K2017/9602—Touch switches characterised by the type or shape of the sensing electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H04B2215/067—Reduction of clock or synthesizer reference frequency harmonics by modulation dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Meat, Egg Or Seafood Products (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
BR9406096A 1993-03-01 1994-02-23 Elemento de retardo diferencial linha de retardo diferencial alinhador de fase sincronizador de bits e controle de função para o mesmo e gerador de referência auto-adaptável BR9406096A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9300679A SE9300679L (sv) 1993-03-01 1993-03-01 Bitsynkroniserare
PCT/SE1994/000151 WO1994021044A1 (en) 1993-03-01 1994-02-23 Bit synchronizer

Publications (1)

Publication Number Publication Date
BR9406096A true BR9406096A (pt) 1995-02-06

Family

ID=20389072

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9406096A BR9406096A (pt) 1993-03-01 1994-02-23 Elemento de retardo diferencial linha de retardo diferencial alinhador de fase sincronizador de bits e controle de função para o mesmo e gerador de referência auto-adaptável

Country Status (16)

Country Link
US (2) US5617452A (pt)
EP (2) EP0687399B1 (pt)
JP (1) JPH08507422A (pt)
KR (1) KR960701511A (pt)
CN (1) CN1132576A (pt)
AU (2) AU683645B2 (pt)
BR (1) BR9406096A (pt)
CA (1) CA2155347A1 (pt)
DE (1) DE69422706T2 (pt)
DK (1) DK0687399T3 (pt)
ES (1) ES2142938T3 (pt)
FI (1) FI954087A (pt)
GR (1) GR3032441T3 (pt)
NO (1) NO953414L (pt)
SE (1) SE9300679L (pt)
WO (1) WO1994021044A1 (pt)

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KR0165404B1 (ko) * 1995-06-17 1999-03-20 이대원 디지탈 신호의 지연방법 및 회로
FR2786632B1 (fr) * 1998-11-27 2002-08-23 Texas Instruments France Procede et dispositif d'alignement de phase a grande vitesse
US6952826B1 (en) * 1999-10-21 2005-10-04 Sony Corporation Method for implementing a multi-level system model for deterministically handling selected data
US6392466B1 (en) * 1999-12-30 2002-05-21 Intel Corporation Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path
KR100366627B1 (ko) * 2000-08-23 2003-01-09 삼성전자 주식회사 Ｄｔｃ 기반 플립플럽 회로 및 비교기
US6885714B1 (en) * 2001-05-24 2005-04-26 Cypress Semiconductor Corp. Independently roving range control
US7082160B2 (en) * 2002-09-05 2006-07-25 Faraday Technology Corp. Pulse width control system for transmitting serial data
US7126986B2 (en) * 2002-09-30 2006-10-24 Intel Corporation Method and system for improved phase tracking
US6838919B1 (en) * 2002-11-19 2005-01-04 Xilinx, Inc. DCVSL pulse width controller and system
JP2005020471A (ja) * 2003-06-27 2005-01-20 Matsushita Electric Ind Co Ltd 調歩同期式通信回路
DE102004044815A1 (de) * 2004-09-16 2006-03-23 Robert Bosch Gmbh Datenverarbeitungsvorrichtung mit Taktrückgewinnung aus unterschiedlichen Quellen
US8073042B1 (en) 2005-04-13 2011-12-06 Cypress Semiconductor Corporation Recursive range controller
WO2009075713A1 (en) * 2007-12-06 2009-06-18 Rambus, Inc. Apparatus and methods for differential signal receiving
CN103425069A (zh) * 2013-08-15 2013-12-04 上海固泰科技有限公司 基于can总线的多设备同步方法
US10218360B2 (en) * 2016-08-02 2019-02-26 Altera Corporation Dynamic clock-data phase alignment in a source synchronous interface circuit
US10630275B2 (en) * 2018-02-26 2020-04-21 Nxp B.V. Constant-on-time pulse generator circuit for a DC-DC converter
CN113093857A (zh) * 2021-03-31 2021-07-09 旋智电子科技（上海）有限公司 一种延迟对称的缓冲分压电路、电压比较电路、接收电路和lin接收机

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119160A (en) * 1976-03-31 1977-10-06 Nec Corp Semiconductor circuit with insulating gate type field dffect transisto r
US4181975A (en) * 1978-07-10 1980-01-01 Rockwell International Corporation Digital delay line apparatus
DE2945331C2 (de) * 1979-11-09 1984-05-30 Nixdorf Computer Ag, 4790 Paderborn Vorrichtung in einer Signal-oder Datenverarbeitungsanlage zur Einstellung einer Signalverarbeitungsschaltung
US4370569A (en) * 1980-10-30 1983-01-25 Hewlett-Packard Company Integratable single pulse circuit
JPS58184817A (ja) * 1982-02-26 1983-10-28 Yokogawa Hewlett Packard Ltd 遅延回路
US4535459A (en) * 1983-05-26 1985-08-13 Rockwell International Corporation Signal detection apparatus
GB2193863B (en) * 1986-07-25 1990-12-12 Plessey Co Plc Improvements relating to data transmission systems
US4756011A (en) * 1986-12-24 1988-07-05 Bell Communications Research, Inc. Digital phase aligner
US4821296A (en) * 1987-08-26 1989-04-11 Bell Communications Research, Inc. Digital phase aligner with outrigger sampling
ATE101769T1 (de) * 1988-10-13 1994-03-15 Siemens Ag Verfahren und schaltungsanordnung zum empfang eines binaeren digitalsignals.
KR920003598B1 (ko) * 1988-12-22 1992-05-04 재단법인 한국전자통신 연구소 Nrz비트 동기방식의 주파수 및 위상검출회로
US5052030A (en) * 1989-05-31 1991-09-24 Siemens Aktiengesellschaft Method for synchronizing a clock, generated with the assistance of a counter, to a reference clock
CA2001266C (en) * 1989-10-23 1996-08-06 John Robert Long Digital phase aligner and method for its operation
US5164677A (en) * 1990-01-16 1992-11-17 Digital Equipment Corporation Method and apparatus for synchronizing signals
EP0511836B1 (en) * 1991-05-01 1997-04-16 Motorola, Inc. Broadband digital phase aligner

Also Published As

Publication number Publication date
EP0687399B1 (en) 2000-01-19
AU6223494A (en) 1994-09-26
KR960701511A (ko) 1996-02-24
SE9300679D0 (sv) 1993-03-01
EP0687399A1 (en) 1995-12-20
AU691230B2 (en) 1998-05-14
DE69422706D1 (de) 2000-02-24
CA2155347A1 (en) 1994-09-15
JPH08507422A (ja) 1996-08-06
DE69422706T2 (de) 2000-06-29
FI954087A0 (fi) 1995-08-31
EP0809375A2 (en) 1997-11-26
ES2142938T3 (es) 2000-05-01
SE9300679L (sv) 1994-09-02
CN1132576A (zh) 1996-10-02
DK0687399T3 (da) 2000-04-17
US5617452A (en) 1997-04-01
FI954087A (fi) 1995-08-31
AU1242097A (en) 1997-03-20
US5692022A (en) 1997-11-25
NO953414L (no) 1995-10-31
NO953414D0 (no) 1995-08-31
AU683645B2 (en) 1997-11-20
GR3032441T3 (en) 2000-05-31
EP0809375A3 (en) 1997-12-10
WO1994021044A1 (en) 1994-09-15

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Legal Events

Date Code Title Description
EE Request for examination
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FA8 Dismissal: dismissal - article 36, par. 1 of industrial property law