BR9103526A - Sistemas de processamento digital dotado de meios melhorados para controle de transferencias de dados a partir de drams de modalidade de pagina - Google Patents

Sistemas de processamento digital dotado de meios melhorados para controle de transferencias de dados a partir de drams de modalidade de pagina

Info

Publication number
BR9103526A
BR9103526A BR919103526A BR9103526A BR9103526A BR 9103526 A BR9103526 A BR 9103526A BR 919103526 A BR919103526 A BR 919103526A BR 9103526 A BR9103526 A BR 9103526A BR 9103526 A BR9103526 A BR 9103526A
Authority
BR
Brazil
Prior art keywords
data transfer
processing systems
transfer control
digital processing
improved means
Prior art date
Application number
BR919103526A
Other languages
English (en)
Inventor
Brian W Curran
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9103526A publication Critical patent/BR9103526A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
BR919103526A 1990-08-31 1991-08-16 Sistemas de processamento digital dotado de meios melhorados para controle de transferencias de dados a partir de drams de modalidade de pagina BR9103526A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/576,252 US5278967A (en) 1990-08-31 1990-08-31 System for providing gapless data transfer from page-mode dynamic random access memories

Publications (1)

Publication Number Publication Date
BR9103526A true BR9103526A (pt) 1992-05-12

Family

ID=24303604

Family Applications (1)

Application Number Title Priority Date Filing Date
BR919103526A BR9103526A (pt) 1990-08-31 1991-08-16 Sistemas de processamento digital dotado de meios melhorados para controle de transferencias de dados a partir de drams de modalidade de pagina

Country Status (4)

Country Link
US (1) US5278967A (pt)
EP (1) EP0473302A3 (pt)
JP (1) JPH0772878B2 (pt)
BR (1) BR9103526A (pt)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69226150T2 (de) 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
US5498990A (en) 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
US5831467A (en) 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
WO1994003901A1 (en) * 1992-08-10 1994-02-17 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5710912A (en) * 1993-05-06 1998-01-20 Hewlett-Packard Co. Method and apparatus for enabling a computer system to adjust for latency assumptions
US5732041A (en) * 1993-08-19 1998-03-24 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US5440523A (en) * 1993-08-19 1995-08-08 Multimedia Communications, Inc. Multiple-port shared memory interface and associated method
US5630086A (en) * 1993-12-03 1997-05-13 Hewlett-Packard Co. Apparatus systems and methods for controlling electronic memories
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
AU5368696A (en) * 1995-03-22 1996-10-08 Ast Research, Inc. Rule-based dram controller
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
TW388982B (en) * 1995-03-31 2000-05-01 Samsung Electronics Co Ltd Memory controller which executes read and write commands out of order
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
US5915128A (en) * 1997-01-29 1999-06-22 Unisys Corporation Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register
US6170046B1 (en) 1997-10-28 2001-01-02 Mmc Networks, Inc. Accessing a memory system via a data or address bus that provides access to more than one part
US6154792A (en) * 1998-06-04 2000-11-28 International Business Machines Corporation Method and computer program product for paging control using a reference structure including a reference bitmap
US6304923B1 (en) 1998-10-14 2001-10-16 Micron Technology, Inc. Method for prioritizing data transfer request by comparing a latency identifier value received from an I/O device with a predetermined range of values
US6266718B1 (en) * 1998-10-14 2001-07-24 Micron Technology, Inc. Apparatus for controlling data transfer operations between a memory and devices having respective latencies
US6625685B1 (en) 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
US6785793B2 (en) * 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
TWI369611B (en) * 2008-08-14 2012-08-01 Asustek Comp Inc Main board and interface control method for memory slot thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1774258A1 (de) * 1968-05-13 1971-09-09 Elektronische Rechenmasch Ind Verfahren zur Adressierung eines Speichers
US4099253A (en) * 1976-09-13 1978-07-04 Dynage, Incorporated Random access memory with bit or byte addressing capability
US4667313A (en) * 1985-01-22 1987-05-19 Texas Instruments Incorporated Serially accessed semiconductor memory with tapped shift register
US4716545A (en) * 1985-03-19 1987-12-29 Wang Laboratories, Inc. Memory means with multiple word read and single word write
US4823324A (en) * 1985-09-23 1989-04-18 Ncr Corporation Page mode operation of main system memory in a medium scale computer
US4992979A (en) * 1985-10-28 1991-02-12 International Business Machines Corporation Memory structure for nonsequential storage of block bytes in multi bit chips
US4796222A (en) * 1985-10-28 1989-01-03 International Business Machines Corporation Memory structure for nonsequential storage of block bytes in multi-bit chips
JPS6314395A (ja) * 1986-07-04 1988-01-21 Nec Corp 記憶回路
US4845664A (en) * 1986-09-15 1989-07-04 International Business Machines Corp. On-chip bit reordering structure
US4903217A (en) * 1987-02-12 1990-02-20 International Business Machines Corp. Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor
DE3786080D1 (de) * 1987-08-20 1993-07-08 Ibm Speicherzugriffssteuerungsvorrichtung in einem gemischtdatenformatsystem.
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US5159676A (en) * 1988-12-05 1992-10-27 Micron Technology, Inc. Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws
US5121354A (en) * 1990-03-12 1992-06-09 International Business Machines Corp. Random access memory with access on bit boundaries

Also Published As

Publication number Publication date
JPH04245347A (ja) 1992-09-01
EP0473302A3 (en) 1992-06-03
JPH0772878B2 (ja) 1995-08-02
US5278967A (en) 1994-01-11
EP0473302A2 (en) 1992-03-04

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Legal Events

Date Code Title Description
KF Request for proof of payment of annual fee
FD5 Application fees: dismissal - article 86 of industrial property law