BR8700180A - Processo para registrar mudancas no estado de paginas virtuais em um sistema de processamento de dados de memoria virtual - Google Patents

Processo para registrar mudancas no estado de paginas virtuais em um sistema de processamento de dados de memoria virtual

Info

Publication number
BR8700180A
BR8700180A BR8700180A BR8700180A BR8700180A BR 8700180 A BR8700180 A BR 8700180A BR 8700180 A BR8700180 A BR 8700180A BR 8700180 A BR8700180 A BR 8700180A BR 8700180 A BR8700180 A BR 8700180A
Authority
BR
Brazil
Prior art keywords
state
memory data
virtual
register changes
processing
Prior art date
Application number
BR8700180A
Other languages
English (en)
Portuguese (pt)
Inventor
John Thomas Ii O'quin
John Claude O'quin Iii
Mark Douglass Rogers
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8700180A publication Critical patent/BR8700180A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR8700180A 1986-01-16 1987-01-16 Processo para registrar mudancas no estado de paginas virtuais em um sistema de processamento de dados de memoria virtual BR8700180A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/819,457 US4730249A (en) 1986-01-16 1986-01-16 Method to operate on large segments of data in a virtual memory data processing system

Publications (1)

Publication Number Publication Date
BR8700180A true BR8700180A (pt) 1987-12-01

Family

ID=25228214

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8700180A BR8700180A (pt) 1986-01-16 1987-01-16 Processo para registrar mudancas no estado de paginas virtuais em um sistema de processamento de dados de memoria virtual

Country Status (5)

Country Link
US (1) US4730249A (enExample)
EP (1) EP0230354B1 (enExample)
JP (1) JPS62229446A (enExample)
BR (1) BR8700180A (enExample)
DE (1) DE3750337T2 (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922414A (en) * 1982-12-17 1990-05-01 Symbolics Inc. Symbolic language data processing system
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US4761737A (en) * 1986-01-16 1988-08-02 International Business Machines Corporation Method to automatically increase the segment size of unix files in a page segmented virtual memory data processing system
US4991078A (en) * 1987-09-29 1991-02-05 Digital Equipment Corporation Apparatus and method for a pipelined central processing unit in a data processing system
US4862349A (en) * 1987-10-19 1989-08-29 International Business Machines Corporation Method for extracting and/or replacing control system information in a computer operating system
US5127094A (en) * 1987-11-09 1992-06-30 Hitachi, Ltd. Virtual storage type computer system
US5239643A (en) * 1987-11-30 1993-08-24 International Business Machines Corporation Method for reducing disk I/O accesses in a multi-processor clustered type data processing system
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
US5055999A (en) 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5341483A (en) * 1987-12-22 1994-08-23 Kendall Square Research Corporation Dynamic hierarchial associative memory
US5761413A (en) * 1987-12-22 1998-06-02 Sun Microsystems, Inc. Fault containment system for multiprocessor with shared memory
US5822578A (en) * 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
JPH0290330A (ja) * 1988-09-28 1990-03-29 Hitachi Ltd プログラム構成方式
CN1016743B (zh) * 1988-12-03 1992-05-20 国际商业机器公司 虚拟存储器管理系统和方法
JPH0373037A (ja) * 1989-05-26 1991-03-28 Hitachi Ltd データベース障害回復方法
US5101485B1 (en) * 1989-06-29 1996-12-10 Frank L Perazzoli Jr Virtual memory page table paging apparatus and method
US5339398A (en) * 1989-07-31 1994-08-16 North American Philips Corporation Memory architecture and method of data organization optimized for hashing
FR2652926B1 (fr) * 1989-10-06 1994-07-08 Bull Sa Procede d'exploitation de la memoire dans un systeme informatique du type a adressage virtuel et dispositif pour la mise en óoeuvre dudit procede.
US5121483A (en) * 1990-05-21 1992-06-09 International Business Machines Corporation Virtual drives in an automated storage library
US5426779A (en) * 1991-09-13 1995-06-20 Salient Software, Inc. Method and apparatus for locating longest prior target string matching current string in buffer
CA2078310A1 (en) * 1991-09-20 1993-03-21 Mark A. Kaufman Digital processor with distributed memory system
CA2078312A1 (en) 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
CA2078315A1 (en) * 1991-09-20 1993-03-21 Christopher L. Reeve Parallel processing apparatus and method for utilizing tiling
US5388244A (en) * 1992-09-17 1995-02-07 International Business Machines Corporation Controls for initial diversion of page-frame logical content as part of dynamic virtual-to-real translation of a virtual page address
US6091430A (en) * 1993-03-31 2000-07-18 International Business Machines Corporation Simultaneous high resolution display within multiple virtual DOS applications in a data processing system
US5586325A (en) * 1993-12-10 1996-12-17 Cray Research, Inc. Method for the dynamic allocation of array sizes in a multiprocessor system
JPH07182239A (ja) * 1993-12-24 1995-07-21 Nec Corp セグメント分割管理システム
US5613068A (en) * 1994-06-17 1997-03-18 International Business Machines Corporation Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's
US5721917A (en) * 1995-01-30 1998-02-24 Hewlett-Packard Company System and method for determining a process's actual working set and relating same to high level data structures
US5699543A (en) * 1995-09-29 1997-12-16 Intel Corporation Profile guided TLB and cache optimization
US7603442B2 (en) * 2003-06-20 2009-10-13 Microsoft Corporation Method and system for maintaining service dependency relationships in a computer system
US7406694B2 (en) * 2003-06-20 2008-07-29 Microsoft Corporation Method and system for tracking kernel resource usage
US7076632B2 (en) * 2003-10-16 2006-07-11 International Business Machines Corporation Fast paging of a large memory block
US9164915B2 (en) 2013-01-15 2015-10-20 International Business Machines Corporation Reserving fixed page areas in real storage increments
US8966220B2 (en) 2013-01-15 2015-02-24 International Business Machines Corporation Optimizing large page processing
US9798673B2 (en) * 2013-03-14 2017-10-24 Sandisk Technologies Llc Paging enablement of storage translation metadata
US9483400B2 (en) * 2014-04-21 2016-11-01 Microsoft Technology Licensing, Llc Multiplexed memory for segments and pages
US11150928B2 (en) * 2016-06-08 2021-10-19 Red Hat Israel, Ltd. Hypervisor translation bypass

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4173783A (en) * 1975-06-30 1979-11-06 Honeywell Information Systems, Inc. Method of accessing paged memory by an input-output unit
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4532590A (en) * 1980-04-25 1985-07-30 Data General Corporation Data processing system having a unique address translation unit
EP0150522B1 (en) * 1980-04-25 1989-08-30 Data General Corporation Data processing system with hierarchical memory protection
JPS5718070A (en) * 1980-07-04 1982-01-29 Fujitsu Ltd Multiplex virtual storage controlling system
US4374417A (en) * 1981-02-05 1983-02-15 International Business Machines Corp. Method for using page addressing mechanism
US4442487A (en) * 1981-12-31 1984-04-10 International Business Machines Corporation Three level memory hierarchy using write and share flags
US4654777A (en) * 1982-05-25 1987-03-31 Tokyo Shibaura Denki Kabushiki Kaisha Segmented one and two level paging address translation system
US4525778A (en) * 1982-05-25 1985-06-25 Massachusetts Computer Corporation Computer memory control
US4569018A (en) * 1982-11-15 1986-02-04 Data General Corp. Digital data processing system having dual-purpose scratchpad and address translation memory
JPS6084641A (ja) * 1983-10-05 1985-05-14 Mitsubishi Electric Corp 仮想計算機システム

Also Published As

Publication number Publication date
DE3750337D1 (de) 1994-09-15
DE3750337T2 (de) 1995-03-09
JPS62229446A (ja) 1987-10-08
US4730249A (en) 1988-03-08
JPH0566621B2 (enExample) 1993-09-22
EP0230354A2 (en) 1987-07-29
EP0230354B1 (en) 1994-08-10
EP0230354A3 (en) 1990-05-30

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Legal Events

Date Code Title Description
FB19 Grant procedure suspended (art. 19)
FF Decision: intention to grant
KD Notifcation of receipt (letter patent)
FA11 Dismissal: dismissal - article 38, par. 2 of industrial property law