BR8505210A - Sistema microprogramavel de arquitetura da palavra da memoria de controle distribuida - Google Patents

Sistema microprogramavel de arquitetura da palavra da memoria de controle distribuida

Info

Publication number
BR8505210A
BR8505210A BR8505210A BR8505210A BR8505210A BR 8505210 A BR8505210 A BR 8505210A BR 8505210 A BR8505210 A BR 8505210A BR 8505210 A BR8505210 A BR 8505210A BR 8505210 A BR8505210 A BR 8505210A
Authority
BR
Brazil
Prior art keywords
microinstruction
control
read
subunits
control store
Prior art date
Application number
BR8505210A
Other languages
English (en)
Inventor
Richard P Kelly
Thomas F Joyce
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of BR8505210A publication Critical patent/BR8505210A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Computer And Data Communications (AREA)
  • Steam Or Hot-Water Central Heating Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Debugging And Monitoring (AREA)
  • Processes Of Treating Macromolecular Substances (AREA)
  • Manufacture, Treatment Of Glass Fibers (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Multi Processors (AREA)
  • Ceramic Products (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Logic Circuits (AREA)
  • Circuits Of Receivers In General (AREA)
BR8505210A 1984-10-19 1985-10-18 Sistema microprogramavel de arquitetura da palavra da memoria de controle distribuida BR8505210A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/663,096 US4670835A (en) 1984-10-19 1984-10-19 Distributed control store word architecture

Publications (1)

Publication Number Publication Date
BR8505210A true BR8505210A (pt) 1986-07-29

Family

ID=24660454

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8505210A BR8505210A (pt) 1984-10-19 1985-10-18 Sistema microprogramavel de arquitetura da palavra da memoria de controle distribuida

Country Status (15)

Country Link
US (1) US4670835A (pt)
EP (1) EP0178671B1 (pt)
JP (1) JPH081595B2 (pt)
KR (1) KR910008918B1 (pt)
CN (1) CN1010259B (pt)
AT (1) ATE64482T1 (pt)
AU (1) AU579194B2 (pt)
BR (1) BR8505210A (pt)
CA (1) CA1240800A (pt)
DE (1) DE3583201D1 (pt)
DK (1) DK165528C (pt)
ES (1) ES8800459A1 (pt)
FI (1) FI87283C (pt)
NO (1) NO169925C (pt)
YU (1) YU45924B (pt)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4802088A (en) * 1986-08-11 1989-01-31 Amdahl Corporation Method and apparatus for performing a pseudo branch in a microword controlled computer system
US4914576A (en) * 1986-12-18 1990-04-03 Bull Hn Information Systems Inc. Apparatus and method of loading a control store memory of a central subsystem
US5148530A (en) * 1987-05-19 1992-09-15 Bull Hn Information Systems Inc. Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits
US4901222A (en) * 1987-05-19 1990-02-13 Bull Nh Information Systems Inc. Method and apparatus for backing out of a software instruction after execution has begun
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
FR2656442B1 (fr) * 1989-12-21 1994-07-29 Bull Sa Processeur a plusieurs unites microprogrammees avec mecanisme d'execution anticipee des instructions.
JP2570466B2 (ja) * 1990-05-18 1997-01-08 日本電気株式会社 情報処理装置
EP0477599A3 (en) * 1990-09-26 1993-11-10 Siemens Ag Control store for a processor comprising several processing elements
US5377335A (en) * 1991-08-30 1994-12-27 Unisys Corporation Multiple alternate path pipelined microsequencer and method for controlling a computer
EP0586767A1 (en) * 1992-09-11 1994-03-16 International Business Machines Corporation Selective data capture for software exception conditions
US5440703A (en) * 1993-09-20 1995-08-08 International Business Machines Corporation System and method for saving state information in a multi-execution unit processor when interruptable instructions are identified
TW436693B (en) * 1998-08-18 2001-05-28 Ind Tech Res Inst Interrupt control device and method for pipeline processor
US7743232B2 (en) 2007-07-18 2010-06-22 Advanced Micro Devices, Inc. Multiple-core processor with hierarchical microcode store
CN101989193B (zh) * 2010-11-05 2013-05-15 青岛海信信芯科技有限公司 微控制器及其指令执行方法
US11467838B2 (en) 2018-05-22 2022-10-11 Advanced Micro Devices, Inc. Fastpath microcode sequencer
US11016763B2 (en) 2019-03-08 2021-05-25 Advanced Micro Devices, Inc. Implementing a micro-operation cache with compaction

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605977B2 (ja) * 1974-05-15 1985-02-15 日本電気株式会社 マイクロプログラム制御装置
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
DE2555963C2 (de) * 1975-12-12 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Funktionsmodifizierung
US4149243A (en) * 1977-10-20 1979-04-10 International Business Machines Corporation Distributed control architecture with post and wait logic
US4268908A (en) * 1979-02-26 1981-05-19 International Business Machines Corporation Modular macroprocessing system comprising a microprocessor and an extendable number of programmed logic arrays
US4393465A (en) * 1981-04-13 1983-07-12 Burroughs Corporation Digital device for time-multiplexing multiple tasks
JPS5851353A (ja) * 1981-09-24 1983-03-26 Nippon Telegr & Teleph Corp <Ntt> プログラム制御回路

Also Published As

Publication number Publication date
KR860003552A (ko) 1986-05-26
FI854043L (fi) 1986-04-20
ES8800459A1 (es) 1987-11-01
ATE64482T1 (de) 1991-06-15
AU579194B2 (en) 1988-11-17
JPS61118838A (ja) 1986-06-06
CA1240800A (en) 1988-08-16
KR910008918B1 (en) 1991-10-24
FI854043A0 (fi) 1985-10-17
FI87283B (fi) 1992-08-31
EP0178671A2 (en) 1986-04-23
DK165528B (da) 1992-12-07
DK165528C (da) 1993-04-19
EP0178671A3 (en) 1988-08-17
YU166785A (en) 1988-02-29
AU4876785A (en) 1986-04-24
EP0178671B1 (en) 1991-06-12
ES548005A0 (es) 1987-11-01
CN85108466A (zh) 1987-04-15
NO169925B (no) 1992-05-11
FI87283C (fi) 1992-12-10
YU45924B (sh) 1992-09-07
DE3583201D1 (de) 1991-07-18
CN1010259B (zh) 1990-10-31
NO169925C (no) 1992-08-19
NO854150L (no) 1986-04-21
US4670835A (en) 1987-06-02
JPH081595B2 (ja) 1996-01-10
DK479085A (da) 1986-04-20
DK479085D0 (da) 1985-10-18

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)