BR8301430A - Metodo de particao de conjuntos de instrucoes de unidades principais para a implementacao da emulsao dos mesmos,baseada em microprocessador - Google Patents

Metodo de particao de conjuntos de instrucoes de unidades principais para a implementacao da emulsao dos mesmos,baseada em microprocessador

Info

Publication number
BR8301430A
BR8301430A BR8301430A BR8301430A BR8301430A BR 8301430 A BR8301430 A BR 8301430A BR 8301430 A BR8301430 A BR 8301430A BR 8301430 A BR8301430 A BR 8301430A BR 8301430 A BR8301430 A BR 8301430A
Authority
BR
Brazil
Prior art keywords
emulsion
microprocessor
implementation
same
instruction sets
Prior art date
Application number
BR8301430A
Other languages
English (en)
Inventor
Palmer Wright Agnew
Joseph Patrick Buonomo
Steven Ray Houghtalen
Anne Sheila Kellerman
Raymond Ellison Losinger
James William Valashinas
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8301430A publication Critical patent/BR8301430A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Executing Machine-Instructions (AREA)
BR8301430A 1982-04-26 1983-03-21 Metodo de particao de conjuntos de instrucoes de unidades principais para a implementacao da emulsao dos mesmos,baseada em microprocessador BR8301430A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/371,634 US4514803A (en) 1982-04-26 1982-04-26 Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof

Publications (1)

Publication Number Publication Date
BR8301430A true BR8301430A (pt) 1983-11-29

Family

ID=23464784

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8301430A BR8301430A (pt) 1982-04-26 1983-03-21 Metodo de particao de conjuntos de instrucoes de unidades principais para a implementacao da emulsao dos mesmos,baseada em microprocessador

Country Status (6)

Country Link
US (1) US4514803A (pt)
EP (1) EP0092610A3 (pt)
JP (1) JPS58191044A (pt)
BR (1) BR8301430A (pt)
CA (1) CA1182573A (pt)
ES (1) ES521806A0 (pt)

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US5025364A (en) * 1987-06-29 1991-06-18 Hewlett-Packard Company Microprocessor emulation system with memory mapping using variable definition and addressing of memory space
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
US4951195A (en) * 1988-02-01 1990-08-21 International Business Machines Corporation Condition code graph analysis for simulating a CPU processor
US5077657A (en) * 1989-06-15 1991-12-31 Unisys Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor
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US5430862A (en) * 1990-06-29 1995-07-04 Bull Hn Information Systems Inc. Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution
US5280595A (en) * 1990-10-05 1994-01-18 Bull Hn Information Systems Inc. State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
US5263034A (en) * 1990-10-09 1993-11-16 Bull Information Systems Inc. Error detection in the basic processing unit of a VLSI central processor
US5226164A (en) * 1991-04-24 1993-07-06 International Business Machines Corporation Millicode register management and pipeline reset
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
EP0567971B1 (en) * 1992-04-27 1999-07-28 Sony Corporation Information processing system assuring compatibility between different models
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5781750A (en) * 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
GB2307072B (en) 1994-06-10 1998-05-13 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5632028A (en) * 1995-03-03 1997-05-20 Hal Computer Systems, Inc. Hardware support for fast software emulation of unimplemented instructions
US5819063A (en) * 1995-09-11 1998-10-06 International Business Machines Corporation Method and data processing system for emulating a program
US5812823A (en) * 1996-01-02 1998-09-22 International Business Machines Corporation Method and system for performing an emulation context save and restore that is transparent to the operating system
US5784638A (en) * 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US6356995B2 (en) * 1998-07-02 2002-03-12 Picoturbo, Inc. Microcode scalable processor
US6366998B1 (en) * 1998-10-14 2002-04-02 Conexant Systems, Inc. Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
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US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7941647B2 (en) * 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US8065504B2 (en) * 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US8127121B2 (en) * 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US6763452B1 (en) 1999-01-28 2004-07-13 Ati International Srl Modifying program execution based on profiling
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
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US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7020600B2 (en) * 2001-09-07 2006-03-28 Texas Instruments Incorporated Apparatus and method for improvement of communication between an emulator unit and a host device
US7331040B2 (en) * 2002-02-06 2008-02-12 Transitive Limted Condition code flag emulation for program code conversion
GB0202728D0 (en) * 2002-02-06 2002-03-27 Transitive Technologies Ltd Condition code flag emulation for program code conversion
US7221763B2 (en) * 2002-04-24 2007-05-22 Silicon Storage Technology, Inc. High throughput AES architecture
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US7401207B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Apparatus and method for adjusting instruction thread priority in a multi-thread processor
US7360062B2 (en) * 2003-04-25 2008-04-15 International Business Machines Corporation Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
US7401208B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor
CN100342319C (zh) * 2005-09-29 2007-10-10 威盛电子股份有限公司 磁盘阵列写入指令处理方法
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US4342083A (en) * 1980-02-05 1982-07-27 The Bendix Corporation Communication system for a multiple-computer system
JPS5833975B2 (ja) * 1980-07-30 1983-07-23 富士通株式会社 デ−タ処理システム

Also Published As

Publication number Publication date
ES8404073A1 (es) 1984-04-01
ES521806A0 (es) 1984-04-01
JPS58191044A (ja) 1983-11-08
CA1182573A (en) 1985-02-12
US4514803A (en) 1985-04-30
EP0092610A3 (en) 1985-05-29
EP0092610A2 (en) 1983-11-02

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