ES8404073A1 - Un metodo para emulacion ejecutada por microprocesador de un computador principal. - Google Patents

Un metodo para emulacion ejecutada por microprocesador de un computador principal.

Info

Publication number
ES8404073A1
ES8404073A1 ES521806A ES521806A ES8404073A1 ES 8404073 A1 ES8404073 A1 ES 8404073A1 ES 521806 A ES521806 A ES 521806A ES 521806 A ES521806 A ES 521806A ES 8404073 A1 ES8404073 A1 ES 8404073A1
Authority
ES
Spain
Prior art keywords
microprocessor
implemented
partitioning
microprocessors
subset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES521806A
Other languages
English (en)
Other versions
ES521806A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8404073A1 publication Critical patent/ES8404073A1/es
Publication of ES521806A0 publication Critical patent/ES521806A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PROCEDIMIENTO DE EMULACION DE ARQUITECTURA DE ORDENADOR A PARTIR DE MICROPROCESADORES.EL CONJUNTO DE INSTRUCCIONES DE ORDENADOR PRINCIPAL ES SUBDIVIDIDO EN VARIOS SUBCONJUNTOS, CADA UNO DE LOS CUALES PUEDE SER EJECUTADO POR UN MICROPROCESADOR QUE TIENE MICROCODIGO ESPECIAL INCORPORADO EN PLAQUITA, O MEDIANTE UN MICROPROCESADOR COMERCIAL NORMALIZADO. ADICIONALMENTE, UN SUBCONJUNTO DEL CONJUNTO DE INSTRUCCIONES SUBDIVIDIDO PUEDE SER IMPLEMENTADO POR PROGRAMAS DE EMULACION, POR MICROCODIGO VERTICAL U HORIZONTAL FUERA DE PLAQUITA, O POR INSTRUCCIONES ORIGINALES.
ES521806A 1982-04-26 1983-04-25 Un metodo para emulacion ejecutada por microprocesador de un computador principal. Granted ES521806A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/371,634 US4514803A (en) 1982-04-26 1982-04-26 Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof

Publications (2)

Publication Number Publication Date
ES8404073A1 true ES8404073A1 (es) 1984-04-01
ES521806A0 ES521806A0 (es) 1984-04-01

Family

ID=23464784

Family Applications (1)

Application Number Title Priority Date Filing Date
ES521806A Granted ES521806A0 (es) 1982-04-26 1983-04-25 Un metodo para emulacion ejecutada por microprocesador de un computador principal.

Country Status (6)

Country Link
US (1) US4514803A (es)
EP (1) EP0092610A3 (es)
JP (1) JPS58191044A (es)
BR (1) BR8301430A (es)
CA (1) CA1182573A (es)
ES (1) ES521806A0 (es)

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US4870614A (en) * 1984-08-02 1989-09-26 Quatse Jesse T Programmable controller ("PC") with co-processing architecture
US4763242A (en) * 1985-10-23 1988-08-09 Hewlett-Packard Company Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
JPS6398038A (ja) * 1986-10-06 1988-04-28 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ処理システム
US5210832A (en) * 1986-10-14 1993-05-11 Amdahl Corporation Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle
US5025364A (en) * 1987-06-29 1991-06-18 Hewlett-Packard Company Microprocessor emulation system with memory mapping using variable definition and addressing of memory space
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
US4951195A (en) * 1988-02-01 1990-08-21 International Business Machines Corporation Condition code graph analysis for simulating a CPU processor
US5077657A (en) * 1989-06-15 1991-12-31 Unisys Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor
EP0432075B1 (en) * 1989-11-09 1997-02-26 International Business Machines Corporation Multiprocessor with relatively atomic instructions
US5430862A (en) * 1990-06-29 1995-07-04 Bull Hn Information Systems Inc. Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution
US5280595A (en) * 1990-10-05 1994-01-18 Bull Hn Information Systems Inc. State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
US5263034A (en) * 1990-10-09 1993-11-16 Bull Information Systems Inc. Error detection in the basic processing unit of a VLSI central processor
US5226164A (en) * 1991-04-24 1993-07-06 International Business Machines Corporation Millicode register management and pipeline reset
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
EP0567971B1 (en) * 1992-04-27 1999-07-28 Sony Corporation Information processing system assuring compatibility between different models
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) * 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5781750A (en) * 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
GB2290395B (en) 1994-06-10 1997-05-28 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5632028A (en) * 1995-03-03 1997-05-20 Hal Computer Systems, Inc. Hardware support for fast software emulation of unimplemented instructions
US5819063A (en) * 1995-09-11 1998-10-06 International Business Machines Corporation Method and data processing system for emulating a program
US5812823A (en) * 1996-01-02 1998-09-22 International Business Machines Corporation Method and system for performing an emulation context save and restore that is transparent to the operating system
US5784638A (en) * 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US6356995B2 (en) 1998-07-02 2002-03-12 Picoturbo, Inc. Microcode scalable processor
US6366998B1 (en) * 1998-10-14 2002-04-02 Conexant Systems, Inc. Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US7111290B1 (en) * 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US8065504B2 (en) * 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8127121B2 (en) * 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) * 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US6826748B1 (en) 1999-01-28 2004-11-30 Ati International Srl Profiling program execution into registers of a computer
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
AU2745001A (en) * 1999-12-31 2001-07-16 Intel Corporation External microcode
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7020600B2 (en) * 2001-09-07 2006-03-28 Texas Instruments Incorporated Apparatus and method for improvement of communication between an emulator unit and a host device
US7331040B2 (en) * 2002-02-06 2008-02-12 Transitive Limted Condition code flag emulation for program code conversion
GB0202728D0 (en) * 2002-02-06 2002-03-27 Transitive Technologies Ltd Condition code flag emulation for program code conversion
US7221763B2 (en) * 2002-04-24 2007-05-22 Silicon Storage Technology, Inc. High throughput AES architecture
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US7401208B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor
US7360062B2 (en) * 2003-04-25 2008-04-15 International Business Machines Corporation Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
US7401207B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Apparatus and method for adjusting instruction thread priority in a multi-thread processor
CN100342319C (zh) * 2005-09-29 2007-10-10 威盛电子股份有限公司 磁盘阵列写入指令处理方法
US7596781B2 (en) * 2006-10-16 2009-09-29 International Business Machines Corporation Register-based instruction optimization for facilitating efficient emulation of an instruction stream
US20240017029A1 (en) * 2020-11-06 2024-01-18 Bon Secours Mercy Health, Inc. Endotracheal tube

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JPS51126020A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Micro program control equipment
US4128876A (en) * 1977-04-28 1978-12-05 International Business Machines Corporation Synchronous microcode generated interface for system of microcoded data processors
JPS5532118A (en) * 1978-08-28 1980-03-06 Fujitsu Ltd Data processing system
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JPS5833975B2 (ja) * 1980-07-30 1983-07-23 富士通株式会社 デ−タ処理システム

Also Published As

Publication number Publication date
US4514803A (en) 1985-04-30
EP0092610A3 (en) 1985-05-29
EP0092610A2 (en) 1983-11-02
BR8301430A (pt) 1983-11-29
JPS58191044A (ja) 1983-11-08
ES521806A0 (es) 1984-04-01
CA1182573A (en) 1985-02-12

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971201