ES520454A0 - Un metodo para seleccionar dos de tres en un sistema de tres computadores. - Google Patents

Un metodo para seleccionar dos de tres en un sistema de tres computadores.

Info

Publication number
ES520454A0
ES520454A0 ES520454A ES520454A ES520454A0 ES 520454 A0 ES520454 A0 ES 520454A0 ES 520454 A ES520454 A ES 520454A ES 520454 A ES520454 A ES 520454A ES 520454 A0 ES520454 A0 ES 520454A0
Authority
ES
Spain
Prior art keywords
selecting
computer system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES520454A
Other languages
English (en)
Other versions
ES8402094A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES520454A0 publication Critical patent/ES520454A0/es
Publication of ES8402094A1 publication Critical patent/ES8402094A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/181—Eliminating the failing redundant component
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Hardware Redundancy (AREA)
ES520454A 1982-03-10 1983-03-10 Un metodo para seleccionar dos de tres en un sistema de tres computadores. Expired ES8402094A1 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3208573A DE3208573C2 (de) 1982-03-10 1982-03-10 2 aus 3-Auswahleinrichtung für ein 3-Rechnersystem
US06/470,756 US4616312A (en) 1982-03-10 1983-02-28 2-out-of-3 Selecting facility in a 3-computer system

Publications (2)

Publication Number Publication Date
ES520454A0 true ES520454A0 (es) 1984-01-01
ES8402094A1 ES8402094A1 (es) 1984-01-01

Family

ID=40908917

Family Applications (1)

Application Number Title Priority Date Filing Date
ES520454A Expired ES8402094A1 (es) 1982-03-10 1983-03-10 Un metodo para seleccionar dos de tres en un sistema de tres computadores.

Country Status (4)

Country Link
US (1) US4616312A (es)
CA (1) CA1199119A (es)
DE (1) DE3208573C2 (es)
ES (1) ES8402094A1 (es)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58221453A (ja) * 1982-06-17 1983-12-23 Toshiba Corp 多重系情報処理装置
DE3639055C2 (de) * 1986-11-14 1998-02-05 Bosch Gmbh Robert Verfahren zur Betriebsüberwachung und Fehlerkorrektur von Rechnern eines Mehrrechnersystems und Mehrrechnersystem
DE3722991A1 (de) * 1987-07-11 1989-01-19 Standard Elektrik Lorenz Ag Verfahren zum zuschalten eines rechners in einem mehrrechnersystem
US4933936A (en) * 1987-08-17 1990-06-12 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Distributed computing system with dual independent communications paths between computers and employing split tokens
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
AU625293B2 (en) * 1988-12-09 1992-07-09 Tandem Computers Incorporated Synchronization of fault-tolerant computer system having multiple processors
US4995040A (en) * 1989-02-03 1991-02-19 Rockwell International Corporation Apparatus for management, comparison, and correction of redundant digital data
JPH0692898B2 (ja) * 1989-05-31 1994-11-16 日本精機株式会社 電子式オドメータ
US5239637A (en) * 1989-06-30 1993-08-24 Digital Equipment Corporation Digital data management system for maintaining consistency of data in a shadow set
US5210865A (en) * 1989-06-30 1993-05-11 Digital Equipment Corporation Transferring data between storage media while maintaining host processor access for I/O operations
US5247618A (en) * 1989-06-30 1993-09-21 Digital Equipment Corporation Transferring data in a digital data processing system
ATE158424T1 (de) * 1989-06-30 1997-10-15 Digital Equipment Corp Verfahren und anordnung zur steuerung von schattenspeichern
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5203004A (en) * 1990-01-08 1993-04-13 Tandem Computers Incorporated Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections
US5382950A (en) * 1990-08-14 1995-01-17 Siemens Aktiengesellschaft Device for implementing an interrupt distribution in a multi-computer system
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
JP3063334B2 (ja) * 1991-12-19 2000-07-12 日本電気株式会社 高信頼度化情報処理装置
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
EP0596410B1 (en) * 1992-11-04 1999-07-28 Digital Equipment Corporation Detection of command synchronisation error
AU5343794A (en) * 1992-11-06 1994-06-08 University Of Newcastle-Upon-Tyne Efficient schemes for constructing reliable computing nodes in distributed systems
DE4407396C2 (de) * 1994-03-05 1999-12-02 Abb Patent Gmbh Verfahren zur Durchführung einer redundanten Signalverarbeitung in 2-von-3 Technik
FR2730074B1 (fr) * 1995-01-27 1997-04-04 Sextant Avionique Architecture de calculateur tolerante aux fautes
US5796935A (en) * 1995-07-20 1998-08-18 Raytheon Company Voting node for a distributed control system
DE19740136A1 (de) * 1997-09-12 1999-03-18 Alsthom Cge Alcatel Verfahren zur Isolation eines defekten Rechners in einem fehlertoleranten Mehrrechnersystem
US6449732B1 (en) 1998-12-18 2002-09-10 Triconex Corporation Method and apparatus for processing control using a multiple redundant processor control system
US6550018B1 (en) * 2000-02-18 2003-04-15 The University Of Akron Hybrid multiple redundant computer system
US6732300B1 (en) 2000-02-18 2004-05-04 Lev Freydel Hybrid triple redundant computer system
US7318169B2 (en) * 2002-05-15 2008-01-08 David Czajkowski Fault tolerant computer
WO2005022280A1 (en) * 2003-09-03 2005-03-10 Unitronics (1989) (R'g) Ltd. System and method for implementing logic control in programmable controllers in distributed control systems
DE102004033263B4 (de) 2004-07-09 2007-07-26 Diehl Aerospace Gmbh Steuer-und Regeleinheit
US7602958B1 (en) * 2004-10-18 2009-10-13 Kla-Tencor Corporation Mirror node process verification
DE602005008602D1 (de) * 2005-09-16 2008-09-11 Siemens Transportation Systems Redundanzkontrollverfahren und Vorrichtung für sichere Rechnereinheiten
DE102007054304A1 (de) * 2007-11-08 2009-05-14 Siemens Ag Rechnerarchitektur
CN101710376B (zh) * 2009-12-18 2012-08-22 浙江大学 安全计算机3取2表决方法硬件平台
CN101751532B (zh) * 2009-12-18 2012-12-05 浙江大学 安全计算机平台安全输出的3取2硬件表决方法
JP2017021617A (ja) * 2015-07-13 2017-01-26 株式会社東芝 多重化制御装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1308497A (en) * 1970-09-25 1973-02-21 Marconi Co Ltd Data processing arrangements
DE2202231A1 (de) * 1972-01-18 1973-07-26 Siemens Ag Verarbeitungssystem mit verdreifachten systemeinheiten
GB1434186A (en) * 1972-04-26 1976-05-05 Gen Electric Co Ltd Multiprocessor computer systems
CH556576A (de) * 1973-03-28 1974-11-29 Hasler Ag Einrichtung zur synchronisierung dreier rechner.
US4015246A (en) * 1975-04-14 1977-03-29 The Charles Stark Draper Laboratory, Inc. Synchronous fault tolerant multi-processor system
DE2939487A1 (de) * 1979-09-28 1981-04-16 Siemens AG, 1000 Berlin und 8000 München Rechnerarchitektur auf der basis einer multi-mikrocomputerstruktur als fehlertolerantes system
US4321666A (en) * 1980-02-05 1982-03-23 The Bendix Corporation Fault handler for a multiple computer system
DE3010803C2 (de) * 1980-03-20 1982-10-28 Siemens AG, 1000 Berlin und 8000 München Schalteinrichtung für ein Dreirechner-System in Eisenbahnanlagen
US4375683A (en) * 1980-11-12 1983-03-01 August Systems Fault tolerant computational system and voter circuit
DE3108871A1 (de) * 1981-03-09 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Einrichtung zur funktionspruefung eines mehrrechnersystems

Also Published As

Publication number Publication date
ES8402094A1 (es) 1984-01-01
US4616312A (en) 1986-10-07
DE3208573A1 (de) 1983-09-22
CA1199119A (en) 1986-01-07
DE3208573C2 (de) 1985-06-27

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