BR8105668A - Modulo de entrada-saida para um processador eletronico - Google Patents
Modulo de entrada-saida para um processador eletronicoInfo
- Publication number
- BR8105668A BR8105668A BR8105668A BR8105668A BR8105668A BR 8105668 A BR8105668 A BR 8105668A BR 8105668 A BR8105668 A BR 8105668A BR 8105668 A BR8105668 A BR 8105668A BR 8105668 A BR8105668 A BR 8105668A
- Authority
- BR
- Brazil
- Prior art keywords
- input
- output module
- electronic processor
- processor
- electronic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bus Control (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT24540/80A IT1149252B (it) | 1980-09-09 | 1980-09-09 | Modulo di ingresso-uscita per un elaboratore elettronico |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR8105668A true BR8105668A (pt) | 1982-05-18 |
Family
ID=11213909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR8105668A BR8105668A (pt) | 1980-09-09 | 1981-09-04 | Modulo de entrada-saida para um processador eletronico |
Country Status (5)
| Country | Link |
|---|---|
| BR (1) | BR8105668A (de) |
| DE (1) | DE3135564A1 (de) |
| FR (1) | FR2489986A1 (de) |
| GB (1) | GB2085623A (de) |
| IT (1) | IT1149252B (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5131081A (en) * | 1989-03-23 | 1992-07-14 | North American Philips Corp., Signetics Div. | System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2131787C3 (de) * | 1971-06-26 | 1973-12-20 | Ibm Deutschland Gmbh, 7000 Stuttgart | Schaltungsanordnung zur Fehlerfeststellung bei Datenverarbeitungssystemen |
| SE420360B (sv) * | 1975-06-30 | 1981-09-28 | Honeywell Inf Systems | Databehandlingsanleggning innefattande ett flertal databehandlingsenheter |
| GB1573329A (en) * | 1976-09-29 | 1980-08-20 | Honeywell Inf Systems | Method and apparatu for detecting errors in parity encoded data |
| US4296466A (en) * | 1978-01-23 | 1981-10-20 | Data General Corporation | Data processing system including a separate input/output processor with micro-interrupt request apparatus |
| DE2845218C2 (de) * | 1978-10-17 | 1986-03-27 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Mikroprogrammgesteuerte Ein-/Ausgabeeinrichtung und Verfahren zum Durchführen von Ein-/Ausgabeoperationen |
| IT1100916B (it) * | 1978-11-06 | 1985-09-28 | Honeywell Inf Systems | Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati |
-
1980
- 1980-09-09 IT IT24540/80A patent/IT1149252B/it active
-
1981
- 1981-08-31 FR FR8116566A patent/FR2489986A1/fr not_active Withdrawn
- 1981-09-04 BR BR8105668A patent/BR8105668A/pt unknown
- 1981-09-08 DE DE19813135564 patent/DE3135564A1/de not_active Withdrawn
- 1981-09-09 GB GB8127217A patent/GB2085623A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2489986A1 (fr) | 1982-03-12 |
| IT8024540A0 (it) | 1980-09-09 |
| IT1149252B (it) | 1986-12-03 |
| GB2085623A (en) | 1982-04-28 |
| DE3135564A1 (de) | 1982-05-19 |
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