BR7907419A - Metodo de teste de microplaquetas logicas com gerador de sequencias de teste que efetua decisoes orientadas para os trajetos - Google Patents

Metodo de teste de microplaquetas logicas com gerador de sequencias de teste que efetua decisoes orientadas para os trajetos

Info

Publication number
BR7907419A
BR7907419A BR7907419A BR7907419A BR7907419A BR 7907419 A BR7907419 A BR 7907419A BR 7907419 A BR7907419 A BR 7907419A BR 7907419 A BR7907419 A BR 7907419A BR 7907419 A BR7907419 A BR 7907419A
Authority
BR
Brazil
Prior art keywords
sequence generator
test method
makes path
test
test sequence
Prior art date
Application number
BR7907419A
Other languages
English (en)
Inventor
Goel Prabhakar
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR7907419A publication Critical patent/BR7907419A/pt

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
BR7907419A 1978-11-20 1979-11-14 Metodo de teste de microplaquetas logicas com gerador de sequencias de teste que efetua decisoes orientadas para os trajetos BR7907419A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/962,431 US4204633A (en) 1978-11-20 1978-11-20 Logic chip test system with path oriented decision making test pattern generator

Publications (1)

Publication Number Publication Date
BR7907419A true BR7907419A (pt) 1980-08-05

Family

ID=25505856

Family Applications (1)

Application Number Title Priority Date Filing Date
BR7907419A BR7907419A (pt) 1978-11-20 1979-11-14 Metodo de teste de microplaquetas logicas com gerador de sequencias de teste que efetua decisoes orientadas para os trajetos

Country Status (5)

Country Link
US (1) US4204633A (pt)
JP (1) JPS5918744B2 (pt)
AU (1) AU5294279A (pt)
BR (1) BR7907419A (pt)
CA (1) CA1139372A (pt)

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Publication number Priority date Publication date Assignee Title
US4308616A (en) * 1979-05-29 1981-12-29 Timoc Constantin C Structure for physical fault simulation of digital logic
GB2070300B (en) * 1980-02-27 1984-01-25 Racal Automation Ltd Electrical testing apparatus and methods
US4356413A (en) * 1980-08-20 1982-10-26 Ibm Corporation MOSFET Convolved logic
US4429389A (en) 1981-05-26 1984-01-31 Burroughs Corporation Test pattern address generator
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4502127A (en) * 1982-05-17 1985-02-26 Fairchild Camera And Instrument Corporation Test system memory architecture for passing parameters and testing dynamic components
DE3237365A1 (de) * 1982-10-08 1984-04-12 Siemens AG, 1000 Berlin und 8000 München Anordnung zur erzeugung von mustern von pruefsignalen bei einem pruefgeraet
US4553049A (en) * 1983-10-07 1985-11-12 International Business Machines Corporation Oscillation prevention during testing of integrated circuit logic chips
GB8327753D0 (en) * 1983-10-17 1983-11-16 Robinson G D Test generation system
EP0177572A4 (en) * 1984-04-06 1986-09-22 Advanced Micro Devices Inc ACTIVE LEAK RESISTANCE CONTROL TO IMPROVE DIGITAL CONVERGENCE IN AN ELECTRONIC CIRCUIT SIMULATOR WHICH IS LOOKING FOR HYPERACTIVE CIRCUIT SOLUTIONS.
US4696006A (en) * 1984-11-26 1987-09-22 Nec Corporation Method of generating test patterns for logic network devices
US4727313A (en) * 1985-03-08 1988-02-23 International Business Machines Corporation Fault simulation for differential cascode voltage switches
US4716564A (en) * 1985-11-15 1987-12-29 Tektronix, Inc. Method for test generation
US4763289A (en) * 1985-12-31 1988-08-09 International Business Machines Corporation Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
US4759019A (en) * 1986-07-10 1988-07-19 International Business Machines Corporation Programmable fault injection tool
US4853928A (en) * 1987-08-28 1989-08-01 Hewlett-Packard Company Automatic test generator for logic devices
US4901260A (en) * 1987-10-28 1990-02-13 American Telephone And Telegraph Company At&T Bell Laboratories Bounded lag distributed discrete event simulation method and apparatus
US5257268A (en) * 1988-04-15 1993-10-26 At&T Bell Laboratories Cost-function directed search method for generating tests for sequential logic circuits
US5012471A (en) * 1988-09-30 1991-04-30 Texas Instruments Incorporated Value-strength based test pattern generator and process
US4996689A (en) * 1989-02-01 1991-02-26 Vlsi Technology, Inc. Method of generating tests for a combinational logic circuit
US5379303A (en) * 1991-06-19 1995-01-03 Sun Microsystems, Inc. Maximizing improvement to fault coverage of system logic of an integrated circuit with embedded memory arrays
JPH05203708A (ja) * 1992-01-28 1993-08-10 Fujitsu Ltd 順序回路の縮退故障テスト方法
US5410552A (en) * 1992-03-27 1995-04-25 Matsushita Electric Industrial Co., Ltd. Method and apparatus for generating test sequence
US5369604A (en) * 1993-02-05 1994-11-29 Texas Instruments Incorporated Test plan generation for analog integrated circuits
US5475695A (en) * 1993-03-19 1995-12-12 Semiconductor Diagnosis & Test Corporation Automatic failure analysis system
US5602856A (en) * 1993-04-06 1997-02-11 Nippon Telegraph And Telephone Corporation Test pattern generation for logic circuits with reduced backtracking operations
US5548715A (en) * 1994-06-10 1996-08-20 International Business Machines Corporation Analysis of untestable faults using discrete node sets
US5831996A (en) * 1996-10-10 1998-11-03 Lucent Technologies Inc. Digital circuit test generator
US6012157A (en) * 1997-12-03 2000-01-04 Lsi Logic Corporation System for verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information
US6249891B1 (en) * 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus
US6212667B1 (en) * 1998-07-30 2001-04-03 International Business Machines Corporation Integrated circuit test coverage evaluation and adjustment mechanism and method
US6370675B1 (en) * 1998-08-18 2002-04-09 Advantest Corp. Semiconductor integrated circuit design and evaluation system using cycle base timing
US6266787B1 (en) * 1998-10-09 2001-07-24 Agilent Technologies, Inc. Method and apparatus for selecting stimulus locations during limited access circuit test
US6167542A (en) * 1998-11-23 2000-12-26 Lucent Technologies Arrangement for fault detection in circuit interconnections
JP3734392B2 (ja) * 1999-10-29 2006-01-11 松下電器産業株式会社 半導体集積回路の故障検査方法及びレイアウト方法
DE10001484C1 (de) * 2000-01-15 2001-09-27 Daimler Chrysler Ag Vorrichtung zur Nachbildung elektrischer Komponenten
US6789222B2 (en) 2001-01-05 2004-09-07 Yardstick Research, L.L.C. Single-pass methods for generating test patterns for combinational circuits
DE10144455A1 (de) * 2001-09-10 2003-04-03 Infineon Technologies Ag Verfahren zur Prüfung eines Abbilds einer elektrischen Schaltung
US7340660B2 (en) * 2003-10-07 2008-03-04 International Business Machines Corporation Method and system for using statistical signatures for testing high-speed circuits
DE10353698A1 (de) * 2003-11-18 2005-06-09 Infineon Technologies Ag Debugmodus in Leistungsversorgungseinheiten von elektronischen Geräten
JP2006250651A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd テストパターン生成支援装置、テストパターン生成支援方法、テストパターン生成支援プログラム、および記録媒体
AU2006314882A1 (en) * 2005-11-21 2007-05-24 Saxo Bank A/S A financial trading system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE790243A (fr) * 1971-11-08 1973-02-15 Burroughs Corp Procede et appareil de verification de sous-systemes de circuits binaires
US3775598A (en) * 1972-06-12 1973-11-27 Ibm Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3916306A (en) * 1973-09-06 1975-10-28 Ibm Method and apparatus for testing high circuit density devices
US3961250A (en) * 1974-05-08 1976-06-01 International Business Machines Corporation Logic network test system with simulator oriented fault test generator

Also Published As

Publication number Publication date
AU5294279A (en) 1980-05-29
JPS5918744B2 (ja) 1984-04-28
CA1139372A (en) 1983-01-11
US4204633A (en) 1980-05-27
JPS5572259A (en) 1980-05-30

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Legal Events

Date Code Title Description
MK Patent expired

Effective date: 19941114