BE790243A - Procede et appareil de verification de sous-systemes de circuits binaires - Google Patents
Procede et appareil de verification de sous-systemes de circuits binairesInfo
- Publication number
- BE790243A BE790243A BE790243DA BE790243A BE 790243 A BE790243 A BE 790243A BE 790243D A BE790243D A BE 790243DA BE 790243 A BE790243 A BE 790243A
- Authority
- BE
- Belgium
- Prior art keywords
- systems
- binary circuits
- verifying sub
- verifying
- sub
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19631671A | 1971-11-08 | 1971-11-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
BE790243A true BE790243A (fr) | 1973-02-15 |
Family
ID=22724889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE790243D BE790243A (fr) | 1971-11-08 | Procede et appareil de verification de sous-systemes de circuits binaires |
Country Status (3)
Country | Link |
---|---|
US (1) | US3739160A (fr) |
BE (1) | BE790243A (fr) |
GB (1) | GB1370180A (fr) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3976864A (en) * | 1974-09-03 | 1976-08-24 | Hewlett-Packard Company | Apparatus and method for testing digital circuits |
US4012625A (en) * | 1975-09-05 | 1977-03-15 | Honeywell Information Systems, Inc. | Non-logic printed wiring board test system |
US4241416A (en) * | 1977-07-01 | 1980-12-23 | Systron-Donner Corporation | Monitoring apparatus for processor controlled equipment |
US4270178A (en) * | 1977-07-19 | 1981-05-26 | Beckman Instruments, Inc. | Measuring system incorporating self-testing probe circuit and method for checking signal levels at test points within the system |
US4183460A (en) * | 1977-12-23 | 1980-01-15 | Burroughs Corporation | In-situ test and diagnostic circuitry and method for CML chips |
US4313200A (en) * | 1978-08-28 | 1982-01-26 | Takeda Riken Kogyo Kabushikikaisha | Logic test system permitting test pattern changes without dummy cycles |
US4204633A (en) * | 1978-11-20 | 1980-05-27 | International Business Machines Corporation | Logic chip test system with path oriented decision making test pattern generator |
US4498172A (en) * | 1982-07-26 | 1985-02-05 | General Electric Company | System for polynomial division self-testing of digital networks |
US4571724A (en) * | 1983-03-23 | 1986-02-18 | Data I/O Corporation | System for testing digital logic devices |
US7054205B2 (en) * | 2003-10-28 | 2006-05-30 | Agilent Technologies, Inc. | Circuit and method for determining integrated circuit propagation delay |
CN118259141B (zh) * | 2024-05-24 | 2024-09-10 | 西安诺瓦星云科技股份有限公司 | 接收卡测试方法、测试工装、系统及可读存储介质 |
-
0
- BE BE790243D patent/BE790243A/fr not_active IP Right Cessation
-
1971
- 1971-11-08 US US00196316A patent/US3739160A/en not_active Expired - Lifetime
-
1972
- 1972-10-25 GB GB4921272A patent/GB1370180A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1370180A (en) | 1974-10-16 |
US3739160A (en) | 1973-06-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RE | Patent lapsed |
Owner name: BURROUGHS CORP. Effective date: 19891031 |