BR112023018636A2 - Pacote compreendendo ligações de fio acopladas a dispositivos integrados - Google Patents

Pacote compreendendo ligações de fio acopladas a dispositivos integrados

Info

Publication number
BR112023018636A2
BR112023018636A2 BR112023018636A BR112023018636A BR112023018636A2 BR 112023018636 A2 BR112023018636 A2 BR 112023018636A2 BR 112023018636 A BR112023018636 A BR 112023018636A BR 112023018636 A BR112023018636 A BR 112023018636A BR 112023018636 A2 BR112023018636 A2 BR 112023018636A2
Authority
BR
Brazil
Prior art keywords
package
wire connections
integrated devices
coupled
connections coupled
Prior art date
Application number
BR112023018636A
Other languages
English (en)
Inventor
Li-Sheng Weng
Lily Zhao
Rong Zhou
Yangyang Sun
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023018636A2 publication Critical patent/BR112023018636A2/pt

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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92127—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

pacote compreendendo ligações de fio acopladas a dispositivos integrados. a presente invenção fornece um pacote que inclui um substrato compreendendo uma cavidade, um primeiro dispositivo integrado acoplado ao substrato através de uma primeira pluralidade de interconexões de pilar e uma primeira pluralidade de interconexões de solda, um segundo dispositivo integrado acoplado ao substrato através de uma segunda pluralidade de interconexões de pilar e uma segunda pluralidade de interconexões de solda e uma pluralidade de ligações de fio acopladas ao primeiro dispositivo integrado e ao segundo dispositivo integrado, em que a pluralidade de ligações de fio está localizada sobre a cavidade do substrato.
BR112023018636A 2021-03-26 2022-02-25 Pacote compreendendo ligações de fio acopladas a dispositivos integrados BR112023018636A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/213,875 US20220320026A1 (en) 2021-03-26 2021-03-26 Package comprising wire bonds coupled to integrated devices
PCT/US2022/017904 WO2022203810A1 (en) 2021-03-26 2022-02-25 Package comprising wire bonds coupled to integrated devices

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Publication Number Publication Date
BR112023018636A2 true BR112023018636A2 (pt) 2023-10-17

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US (1) US20220320026A1 (pt)
EP (1) EP4315412A1 (pt)
JP (1) JP2024510402A (pt)
KR (1) KR20230161445A (pt)
CN (1) CN116918060A (pt)
BR (1) BR112023018636A2 (pt)
TW (1) TW202303911A (pt)
WO (1) WO2022203810A1 (pt)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220199480A1 (en) * 2020-12-21 2022-06-23 Intel Corporation Microelectronic structures including bridges
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872325B2 (en) * 2009-02-24 2011-01-18 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Reduced-crosstalk wirebonding in an optical communication system
JP5509724B2 (ja) * 2009-08-20 2014-06-04 富士通株式会社 マルチチップモジュールの製造方法
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US10037970B2 (en) * 2016-09-08 2018-07-31 Nxp Usa, Inc. Multiple interconnections between die
US10515921B2 (en) * 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US10797022B2 (en) * 2017-10-06 2020-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10535608B1 (en) * 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
US11532595B2 (en) * 2021-03-02 2022-12-20 Micron Technology, Inc. Stacked semiconductor dies for semiconductor device assemblies

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JP2024510402A (ja) 2024-03-07
US20220320026A1 (en) 2022-10-06
KR20230161445A (ko) 2023-11-27
TW202303911A (zh) 2023-01-16
WO2022203810A1 (en) 2022-09-29
EP4315412A1 (en) 2024-02-07
CN116918060A (zh) 2023-10-20

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