BR112023014688A2 - Pacote com um substrato compreendendo interconexões de periferia - Google Patents

Pacote com um substrato compreendendo interconexões de periferia

Info

Publication number
BR112023014688A2
BR112023014688A2 BR112023014688A BR112023014688A BR112023014688A2 BR 112023014688 A2 BR112023014688 A2 BR 112023014688A2 BR 112023014688 A BR112023014688 A BR 112023014688A BR 112023014688 A BR112023014688 A BR 112023014688A BR 112023014688 A2 BR112023014688 A2 BR 112023014688A2
Authority
BR
Brazil
Prior art keywords
substrate
package
integrated device
interconnections
periphery
Prior art date
Application number
BR112023014688A
Other languages
English (en)
Portuguese (pt)
Inventor
Aniket Patil
Bok We Hong
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023014688A2 publication Critical patent/BR112023014688A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/862—Bump connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
BR112023014688A 2021-02-01 2021-12-22 Pacote com um substrato compreendendo interconexões de periferia BR112023014688A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/164,723 US11749611B2 (en) 2021-02-01 2021-02-01 Package with a substrate comprising periphery interconnects
PCT/US2021/064902 WO2022164559A1 (en) 2021-02-01 2021-12-22 Package with a substrate comprising periphery interconnects

Publications (1)

Publication Number Publication Date
BR112023014688A2 true BR112023014688A2 (pt) 2023-12-12

Family

ID=79730483

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023014688A BR112023014688A2 (pt) 2021-02-01 2021-12-22 Pacote com um substrato compreendendo interconexões de periferia

Country Status (8)

Country Link
US (1) US11749611B2 (https=)
EP (1) EP4285411A1 (https=)
JP (1) JP7789073B2 (https=)
KR (1) KR20230137330A (https=)
CN (1) CN116783706A (https=)
BR (1) BR112023014688A2 (https=)
TW (1) TW202234633A (https=)
WO (1) WO2022164559A1 (https=)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62100726U (https=) * 1985-12-13 1987-06-26
US6400575B1 (en) 1996-10-21 2002-06-04 Alpine Microsystems, Llc Integrated circuits packaging system and method
JP2000307203A (ja) * 1999-04-22 2000-11-02 Denso Corp 電子部品実装用基板
US6909052B1 (en) * 2002-08-23 2005-06-21 Emc Corporation Techniques for making a circuit board with improved impedance characteristics
JP2008147438A (ja) 2006-12-11 2008-06-26 Nec Electronics Corp 半導体装置
JP4967164B2 (ja) * 2008-03-19 2012-07-04 Ｎｅｃインフロンティア株式会社 多層プリント配線板及びそれを用いた電子機器
US9691694B2 (en) 2015-02-18 2017-06-27 Qualcomm Incorporated Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
CN109564923B (zh) * 2018-06-28 2020-04-28 长江存储科技有限责任公司 具有屏蔽层的三维存储器器件以及用于制造其的方法
CN109219885A (zh) * 2018-07-20 2019-01-15 长江存储科技有限责任公司 三维存储器件
JP7133516B2 (ja) * 2019-06-24 2022-09-08 日立Astemo株式会社 信号伝送回路、電子制御装置
US11201139B2 (en) * 2020-03-20 2021-12-14 Sandisk Technologies Llc Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same
US11444019B2 (en) 2020-04-06 2022-09-13 Qualcomm Incorporated Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package
US11322466B2 (en) * 2020-05-20 2022-05-03 Sandisk Technologies Llc Semiconductor die containing dummy metallic pads and methods of forming the same
US11444039B2 (en) * 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

Also Published As

Publication number Publication date
WO2022164559A1 (en) 2022-08-04
US20220246531A1 (en) 2022-08-04
JP2024505488A (ja) 2024-02-06
US11749611B2 (en) 2023-09-05
KR20230137330A (ko) 2023-10-04
EP4285411A1 (en) 2023-12-06
TW202234633A (zh) 2022-09-01
JP7789073B2 (ja) 2025-12-19
CN116783706A (zh) 2023-09-19

Similar Documents

Publication Publication Date Title
BR112023014695A2 (pt) Pacote tendo um substrato compreendendo interconexões de superfície alinhadas com uma superfície do substrato
US10657851B2 (en) Display device
BR112021016853A2 (pt) Painel de exibição
JP2017058678A5 (ja) 表示装置
JP2017092477A5 (https=)
US11785812B2 (en) Display device including via to release internal stress
BR112022018417A2 (pt) Dispositivo integrado compreendendo transistor acoplado a um contato de base fictícia
JP2018509758A5 (https=)
JP2012190042A5 (https=)
JP2018093197A5 (https=)
BR112022019588A2 (pt) Pacote compreendendo um substrato com interconexão de roteamento sobre camada resistente à solda
JP2014154479A (ja) Ｌｅｄランプ
BR112016006759A2 (pt) processo de obtenção de um substrato revestido com um empilhamento compreendendo uma camada de óxido transparente condutor
BR112023002754A2 (pt) Dispositivo, pacote e/ou substrato compreendendo antena curva
US9839121B2 (en) Electronic device and dynamic random access memory thereof
JP2018200377A5 (https=)
BR112022016578A2 (pt) Pacote de semicondutores compreendendo um substrato e uma estrutura de interconexão de alta densidade acoplada ao mesmo
JPWO2021005434A5 (ja) 表示装置
JP2019175832A5 (ja) 表示パネルおよび表示装置
JP2020522117A5 (https=)
BR112022015520A2 (pt) Pacote compreendendo um substrato configurado como um difusor de calor
JP2017204640A5 (https=)
BR112023014688A2 (pt) Pacote com um substrato compreendendo interconexões de periferia
BR112023019888A2 (pt) Pacote compreendendo componente passivo entre substratos para desempenho de rede de distribuição de energia (pdn) melhorado
US11665819B2 (en) Driving circuit board and display device