BR112021021816A8 - Fabricação de via através de silício em dispositivos quânticos planares - Google Patents
Fabricação de via através de silício em dispositivos quânticos planaresInfo
- Publication number
- BR112021021816A8 BR112021021816A8 BR112021021816A BR112021021816A BR112021021816A8 BR 112021021816 A8 BR112021021816 A8 BR 112021021816A8 BR 112021021816 A BR112021021816 A BR 112021021816A BR 112021021816 A BR112021021816 A BR 112021021816A BR 112021021816 A8 BR112021021816 A8 BR 112021021816A8
- Authority
- BR
- Brazil
- Prior art keywords
- superconducting layer
- silicon
- quantum devices
- path
- planar quantum
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 title abstract 3
- 239000010703 silicon Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/805—Constructional details for Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0241—Manufacture or treatment of devices comprising nitrides or carbonitrides
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N20/00—Machine learning
- G06N20/10—Machine learning using kernel methods, e.g. support vector machines [SVM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32058—Deposition of superconductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53285—Conductive materials containing superconducting materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Medical Informatics (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Artificial Intelligence (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Recrystallisation Techniques (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
fabricação de via através de silício em dispositivos quânticos planares. em uma primeira camada supercondutora (316) depositada em uma primeira superfície de um substrato (312), um primeiro componente de um ressonador é padronizado. em uma segunda camada supercondutora (326) depositada em uma segunda superfície do substrato (312), um segundo componente do ressonador é padronizado. a primeira superfície e a segunda superfície são dispostas em relação uma à outra em uma disposição não coplanar. no substrato, um recesso é criado, o recesso se estendendo da primeira camada supercondutora para a segunda camada supercondutora. em uma superfície interna do recesso, uma terceira camada supercondutora (322) é depositada, a terceira camada supercondutora formando um caminho supercondutor entre a primeira camada supercondutora e a segunda camada supercondutora. o excesso de material da terceira camada supercondutora é removido da primeira superfície e da segunda superfície, formando um uma via através de silício (tsv) completa(320).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/396,992 US11088310B2 (en) | 2019-04-29 | 2019-04-29 | Through-silicon-via fabrication in planar quantum devices |
PCT/EP2020/057766 WO2020221510A1 (en) | 2019-04-29 | 2020-03-20 | Through-silicon-via fabrication in planar quantum devices |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112021021816A2 BR112021021816A2 (pt) | 2022-01-04 |
BR112021021816A8 true BR112021021816A8 (pt) | 2022-01-18 |
Family
ID=70189899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112021021816A BR112021021816A8 (pt) | 2019-04-29 | 2020-03-20 | Fabricação de via através de silício em dispositivos quânticos planares |
Country Status (12)
Country | Link |
---|---|
US (1) | US11088310B2 (pt) |
EP (1) | EP3963635A1 (pt) |
JP (1) | JP7430198B2 (pt) |
KR (1) | KR102574940B1 (pt) |
CN (1) | CN113632233A (pt) |
AU (1) | AU2020265711B2 (pt) |
BR (1) | BR112021021816A8 (pt) |
CA (1) | CA3137245A1 (pt) |
IL (1) | IL287255B2 (pt) |
MX (1) | MX2021012895A (pt) |
SG (1) | SG11202109843RA (pt) |
WO (1) | WO2020221510A1 (pt) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210280763A1 (en) * | 2019-12-23 | 2021-09-09 | Microsoft Technology Licensing, Llc | Superconductor heterostructures for semiconductor-superconductor hybrid structures |
CN113257988B (zh) * | 2020-04-01 | 2022-05-06 | 阿里巴巴集团控股有限公司 | 硬掩模及其制备方法、约瑟夫森结的制备方法及超导电路 |
US11417819B2 (en) * | 2020-04-27 | 2022-08-16 | Microsoft Technology Licensing, Llc | Forming a bumpless superconductor device by bonding two substrates via a dielectric layer |
US11038094B1 (en) * | 2021-01-19 | 2021-06-15 | Quantala LLC | Superconducting qubit with tapered junction wiring |
US11784111B2 (en) | 2021-05-28 | 2023-10-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
US11631631B2 (en) * | 2021-05-28 | 2023-04-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device including via structure for vertical electrical connection |
NL2030907B1 (en) * | 2022-02-11 | 2023-08-18 | Quantware Holding B V | Quantum computing apparatus with interposer, method of fabrication thereof, method of performing a quantum computing operation, quantum computing apparatus comprising tantalum nitride and a method of fabrication thereof |
WO2023188391A1 (ja) * | 2022-03-31 | 2023-10-05 | 富士通株式会社 | 量子デバイス及び量子デバイスの製造方法 |
CN115440879B (zh) * | 2022-06-16 | 2023-04-25 | 合肥本源量子计算科技有限责任公司 | 超导硅片及其制备方法 |
CN118139515A (zh) * | 2024-05-06 | 2024-06-04 | 中国科学技术大学 | 基于通孔结构的超导量子比特器件 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6427294A (en) * | 1987-04-27 | 1989-01-30 | Fujitsu Ltd | Multilayer circuit board for superconducting ceramics circuit and manufacture thereof |
JP2003298232A (ja) | 2002-04-02 | 2003-10-17 | Sony Corp | 多層配線基板の製造方法および多層配線基板 |
US8580682B2 (en) * | 2010-09-30 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cost-effective TSV formation |
US9012322B2 (en) * | 2013-04-05 | 2015-04-21 | Intermolecular, Inc. | Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition |
EP3120460B1 (en) | 2014-03-21 | 2020-10-14 | Google LLC | Chips including classical and quantum computing processors |
US9524470B1 (en) | 2015-06-12 | 2016-12-20 | International Business Machines Corporation | Modular array of vertically integrated superconducting qubit devices for scalable quantum computing |
US10658424B2 (en) * | 2015-07-23 | 2020-05-19 | Massachusetts Institute Of Technology | Superconducting integrated circuit |
US10242968B2 (en) * | 2015-11-05 | 2019-03-26 | Massachusetts Institute Of Technology | Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages |
WO2017079417A1 (en) | 2015-11-05 | 2017-05-11 | Massachusetts Institute Of Technology | Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits |
CN105468821B (zh) | 2015-11-15 | 2018-11-02 | 北京工业大学 | 利用最小包围圆的tsv自动定位方法 |
US10586909B2 (en) * | 2016-10-11 | 2020-03-10 | Massachusetts Institute Of Technology | Cryogenic electronic packages and assemblies |
CN107564868B (zh) | 2017-07-07 | 2019-08-02 | 清华大学 | 一种超导量子计算芯片的集成封装结构和方法 |
US10446736B2 (en) * | 2017-11-27 | 2019-10-15 | International Business Machines Corporation | Backside coupling with superconducting partial TSV for transmon qubits |
US10305015B1 (en) * | 2017-11-30 | 2019-05-28 | International Business Machines Corporation | Low loss architecture for superconducting qubit circuits |
US10243132B1 (en) * | 2018-03-23 | 2019-03-26 | International Business Machines Corporation | Vertical josephson junction superconducting device |
US10497746B1 (en) * | 2018-05-25 | 2019-12-03 | International Business Machines Corporation | Three-dimensional integration for qubits on crystalline dielectric |
-
2019
- 2019-04-29 US US16/396,992 patent/US11088310B2/en active Active
-
2020
- 2020-03-20 CN CN202080021686.6A patent/CN113632233A/zh active Pending
- 2020-03-20 MX MX2021012895A patent/MX2021012895A/es unknown
- 2020-03-20 CA CA3137245A patent/CA3137245A1/en active Pending
- 2020-03-20 KR KR1020217033038A patent/KR102574940B1/ko active IP Right Grant
- 2020-03-20 BR BR112021021816A patent/BR112021021816A8/pt unknown
- 2020-03-20 AU AU2020265711A patent/AU2020265711B2/en active Active
- 2020-03-20 EP EP20717098.6A patent/EP3963635A1/en active Pending
- 2020-03-20 SG SG11202109843R patent/SG11202109843RA/en unknown
- 2020-03-20 WO PCT/EP2020/057766 patent/WO2020221510A1/en unknown
- 2020-03-20 JP JP2021557159A patent/JP7430198B2/ja active Active
-
2021
- 2021-10-13 IL IL287255A patent/IL287255B2/en unknown
Also Published As
Publication number | Publication date |
---|---|
CA3137245A1 (en) | 2020-11-05 |
IL287255B2 (en) | 2023-08-01 |
KR102574940B1 (ko) | 2023-09-04 |
EP3963635A1 (en) | 2022-03-09 |
AU2020265711A1 (en) | 2021-09-30 |
KR20210144761A (ko) | 2021-11-30 |
BR112021021816A2 (pt) | 2022-01-04 |
US20200343434A1 (en) | 2020-10-29 |
JP7430198B2 (ja) | 2024-02-09 |
CN113632233A (zh) | 2021-11-09 |
SG11202109843RA (en) | 2021-10-28 |
AU2020265711B2 (en) | 2023-06-01 |
IL287255A (en) | 2021-12-01 |
IL287255B1 (en) | 2023-04-01 |
WO2020221510A1 (en) | 2020-11-05 |
JP2022530310A (ja) | 2022-06-29 |
MX2021012895A (es) | 2021-12-15 |
US11088310B2 (en) | 2021-08-10 |
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Legal Events
Date | Code | Title | Description |
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B06W | Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette] |