BR112019023301A2 - Construindo matrizes de verificação de paridade com ortogonalidade em linha por códigos qc-ldpc de taxa compatível - Google Patents
Construindo matrizes de verificação de paridade com ortogonalidade em linha por códigos qc-ldpc de taxa compatível Download PDFInfo
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- BR112019023301A2 BR112019023301A2 BR112019023301-6A BR112019023301A BR112019023301A2 BR 112019023301 A2 BR112019023301 A2 BR 112019023301A2 BR 112019023301 A BR112019023301 A BR 112019023301A BR 112019023301 A2 BR112019023301 A2 BR 112019023301A2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
- H04L1/0069—Puncturing patterns
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
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- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
certos aspectos da presente divulgação geralmente se relacionam a métodos e aparelhos para decodificar códigos compatíveis com taxa de verificação de paridade de baixa densidade quase cíclica (qc-ldpc), por exemplo, usando uma matriz de verificação de paridade compreendendo primeiras camadas de acordo com um gráfico de núcleo de alta taxa e segunda camadas para transmissão harq, em que a matriz de verificação de paridade possui quase ortogonalidade de linha ou ortogonalidade de linha completa dentro das segundas camadas. um método exemplar para executar decodificação de verificação de paridade de baixa densidade (ldpc) inclui o recebimento de bits flexíveis associados a uma palavra código ldpc e a execução da decodificação ldpc dos bits flexíveis usando uma matriz de verificação de paridade, em que cada linha da matriz de verificação de paridade corresponde a uma verificação de paridade levantada de um código ldpc levantado, pelo menos duas colunas da matriz de verificação de paridade correspondem a nós variáveis perfurados do código ldpc levantado e a matriz de verificação de paridade tem ortogonalidade de linha entre cada par de linhas consecutivas abaixo de uma linha na qual os pelo menos dois nós variáveis perfurados estão conectados.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762505573P | 2017-05-12 | 2017-05-12 | |
US62/505,573 | 2017-05-12 | ||
US15/975,440 | 2018-05-09 | ||
US15/975,440 US10680646B2 (en) | 2017-05-12 | 2018-05-09 | Row orthogonality in LDPC rate compatible design |
PCT/US2018/031988 WO2018209035A1 (en) | 2017-05-12 | 2018-05-10 | Constructing parity check matrices with row-orthogonality for rate compatible qc-ldpc codes |
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BR112019023301A2 true BR112019023301A2 (pt) | 2020-06-16 |
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BR112019023301-6A BR112019023301A2 (pt) | 2017-05-12 | 2018-05-10 | Construindo matrizes de verificação de paridade com ortogonalidade em linha por códigos qc-ldpc de taxa compatível |
Country Status (9)
Country | Link |
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US (3) | US10680646B2 (pt) |
EP (1) | EP3622627A1 (pt) |
JP (1) | JP6828190B2 (pt) |
KR (1) | KR102197173B1 (pt) |
CN (2) | CN110622425B (pt) |
BR (1) | BR112019023301A2 (pt) |
SG (1) | SG11201909120PA (pt) |
TW (1) | TWI725308B (pt) |
WO (1) | WO2018209035A1 (pt) |
Families Citing this family (11)
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US10680646B2 (en) | 2017-05-12 | 2020-06-09 | Qualcomm Incorporated | Row orthogonality in LDPC rate compatible design |
US10879927B2 (en) * | 2017-05-17 | 2020-12-29 | Futurewei Technologies, Inc. | Compact low density parity check (LDPC) base graph |
CN108988869B (zh) * | 2017-05-31 | 2021-07-30 | 大唐移动通信设备有限公司 | 一种确定校验矩阵的方法及装置、计算机存储介质 |
US10312939B2 (en) | 2017-06-10 | 2019-06-04 | Qualcomm Incorporated | Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code |
WO2019114992A1 (en) * | 2017-12-15 | 2019-06-20 | Huawei Technologies Co., Ltd. | Design of base parity-check matrices for ldpc codes that have subsets of orthogonal rows |
WO2019164515A1 (en) * | 2018-02-23 | 2019-08-29 | Nokia Technologies Oy | Ldpc codes for 3gpp nr ultra-reliable low-latency communications |
US10979072B2 (en) * | 2019-03-19 | 2021-04-13 | Western Digital Technologies, Inc. | Punctured bit estimation and bit error rate estimation |
WO2020218629A1 (ko) * | 2019-04-22 | 2020-10-29 | 엘지전자 주식회사 | 레이트-호환 비이진 ldpc 코드를 지원하기 위한 방법 및 이를 이용한 무선 단말 |
KR20210090483A (ko) | 2020-01-10 | 2021-07-20 | 주식회사 엘지에너지솔루션 | 다공성 환원 그래핀 옥사이드, 이의 제조방법, 이를 포함하는 황-탄소 복합체 및 리튬 이차전지 |
CN112039536B (zh) * | 2020-06-12 | 2023-04-18 | 中山大学 | 一种基于正交频分复用技术的自适应极化码编译码方法 |
US20240097817A1 (en) * | 2021-03-18 | 2024-03-21 | Qualcomm Incorporated | Bit replacing for low density parity check encoding |
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WO2005015748A1 (en) * | 2003-08-08 | 2005-02-17 | Intel Corporation | Method and apparatus for varying lengths of low density parity check codewords |
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-
2018
- 2018-05-09 US US15/975,440 patent/US10680646B2/en active Active
- 2018-05-10 CN CN201880030726.6A patent/CN110622425B/zh active Active
- 2018-05-10 CN CN202410167930.XA patent/CN118018038A/zh active Pending
- 2018-05-10 BR BR112019023301-6A patent/BR112019023301A2/pt unknown
- 2018-05-10 WO PCT/US2018/031988 patent/WO2018209035A1/en active Application Filing
- 2018-05-10 JP JP2019561752A patent/JP6828190B2/ja active Active
- 2018-05-10 SG SG11201909120P patent/SG11201909120PA/en unknown
- 2018-05-10 EP EP18732965.1A patent/EP3622627A1/en active Pending
- 2018-05-10 KR KR1020197033238A patent/KR102197173B1/ko active IP Right Grant
- 2018-05-10 TW TW107115891A patent/TWI725308B/zh active
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2020
- 2020-05-05 US US16/867,330 patent/US11411581B2/en active Active
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2022
- 2022-08-05 US US17/817,717 patent/US11916571B2/en active Active
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US20200266832A1 (en) | 2020-08-20 |
US20230030277A1 (en) | 2023-02-02 |
CN110622425A (zh) | 2019-12-27 |
KR20200003829A (ko) | 2020-01-10 |
EP3622627A1 (en) | 2020-03-18 |
US20190013827A1 (en) | 2019-01-10 |
WO2018209035A1 (en) | 2018-11-15 |
US11916571B2 (en) | 2024-02-27 |
KR102197173B1 (ko) | 2020-12-31 |
TWI725308B (zh) | 2021-04-21 |
US10680646B2 (en) | 2020-06-09 |
SG11201909120PA (en) | 2019-11-28 |
JP6828190B2 (ja) | 2021-02-10 |
CN118018038A (zh) | 2024-05-10 |
JP2020521362A (ja) | 2020-07-16 |
TW201902136A (zh) | 2019-01-01 |
US11411581B2 (en) | 2022-08-09 |
CN110622425B (zh) | 2024-02-20 |
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