BR112018005984A2 - gerenciamento de energia com flip-flops - Google Patents

gerenciamento de energia com flip-flops

Info

Publication number
BR112018005984A2
BR112018005984A2 BR112018005984A BR112018005984A BR112018005984A2 BR 112018005984 A2 BR112018005984 A2 BR 112018005984A2 BR 112018005984 A BR112018005984 A BR 112018005984A BR 112018005984 A BR112018005984 A BR 112018005984A BR 112018005984 A2 BR112018005984 A2 BR 112018005984A2
Authority
BR
Brazil
Prior art keywords
power management
flip
flip flops
flops
power rail
Prior art date
Application number
BR112018005984A
Other languages
English (en)
Inventor
Bhan Divjyot
Pant Harshat
Cao Lipeng
Najdesamii Parissa
Vilangudipitchai Ramaprasath
Pradeep Kochuri Sai
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018005984A2 publication Critical patent/BR112018005984A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

Landscapes

  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

um circuito integrado (ic) é descrito aqui para o gerenciamento de energia com flip-flops possuindo um acessório de retenção. em um aspecto ilustrativo, um ic inclui um trilho de energia constante (kpr), um trilho de energia desmontável (cpr), múltiplos flip-flops (206), e um conjunto de circuitos de gerenciamento de energia (306). cada flip-flop (304) dentre os múltiplos flip-flops inclui uma parte máster (302) que é acoplada ao trilho de energia desmontável (cpr) e uma parte escrava (304) que é acoplada ao trilho de energia constante (kpr). o conjunto de circuitos de gerenciamento de energia (306) é configurado para combinar um sinal de relógio (208) e um sinal de retenção (210) em um sinal de controle combinado (ccs) e para fornecer o sinal de controle combinado para cada flip-flop dentre os múltiplos flip-flops.
BR112018005984A 2015-09-24 2016-08-12 gerenciamento de energia com flip-flops BR112018005984A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/864,101 US9473113B1 (en) 2015-09-24 2015-09-24 Power management with flip-flops
PCT/US2016/046909 WO2017052838A1 (en) 2015-09-24 2016-08-12 Power management with flip-flops

Publications (1)

Publication Number Publication Date
BR112018005984A2 true BR112018005984A2 (pt) 2018-10-09

Family

ID=56889200

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018005984A BR112018005984A2 (pt) 2015-09-24 2016-08-12 gerenciamento de energia com flip-flops

Country Status (7)

Country Link
US (1) US9473113B1 (pt)
EP (1) EP3353891B1 (pt)
JP (1) JP6487115B2 (pt)
KR (1) KR101929193B1 (pt)
CN (1) CN108141205B (pt)
BR (1) BR112018005984A2 (pt)
WO (1) WO2017052838A1 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10404240B2 (en) 2016-01-28 2019-09-03 Samsung Electronics Co., Ltd. Semiconductor device comprising low power retention flip-flop
US10608615B2 (en) * 2016-01-28 2020-03-31 Samsung Electronics Co., Ltd. Semiconductor device including retention reset flip-flop
US10430302B2 (en) 2017-04-12 2019-10-01 Qualcomm Incorporated Data retention with data migration
US10262723B2 (en) * 2017-05-25 2019-04-16 Samsung Electronics Co., Ltd. System and method for improving scan hold-time violation and low voltage operation in sequential circuit
US10852807B2 (en) 2018-02-01 2020-12-01 Microsoft Technology Licensing, Llc Hybrid powering off of storage component memory cells
DE102019106109A1 (de) 2018-04-03 2019-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Datenspeicherschaltung und -verfahren
US11012057B2 (en) * 2018-04-03 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Data retention circuit and method
US10516383B1 (en) * 2018-08-24 2019-12-24 Groq, Inc. Reducing power consumption in a processor circuit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10343565B3 (de) * 2003-09-19 2005-03-10 Infineon Technologies Ag Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7180348B2 (en) * 2005-03-24 2007-02-20 Arm Limited Circuit and method for storing data in operational and sleep modes
US20070085585A1 (en) * 2005-10-13 2007-04-19 Arm Limited Data retention in operational and sleep modes
US7548103B2 (en) 2006-10-26 2009-06-16 Freescale Semiconductor, Inc. Storage device having low power mode and methods thereof
JP2009302903A (ja) 2008-06-13 2009-12-24 Toshiba Corp 半導体集積回路
JP2010282411A (ja) * 2009-06-04 2010-12-16 Renesas Electronics Corp 半導体集積回路、半導体集積回路の内部状態退避回復方法
US8381163B2 (en) * 2010-11-22 2013-02-19 Advanced Micro Devices, Inc. Power-gated retention flops
US8390328B2 (en) * 2011-05-13 2013-03-05 Arm Limited Supplying a clock signal and a gated clock signal to synchronous elements
US8928383B2 (en) * 2013-03-15 2015-01-06 Analog Devices, Inc. Integrated delayed clock for high speed isolated SPI communication
EP2995003A4 (en) * 2013-05-08 2017-03-08 Qualcomm Incorporated Flip-flop for reducing dynamic power
US8841952B1 (en) 2013-05-27 2014-09-23 Freescale Semiconductor, Inc. Data retention flip-flop

Also Published As

Publication number Publication date
EP3353891A1 (en) 2018-08-01
CN108141205A (zh) 2018-06-08
KR20180049142A (ko) 2018-05-10
KR101929193B1 (ko) 2018-12-14
EP3353891B1 (en) 2021-04-07
JP6487115B2 (ja) 2019-03-20
JP2018528710A (ja) 2018-09-27
WO2017052838A1 (en) 2017-03-30
US9473113B1 (en) 2016-10-18
CN108141205B (zh) 2020-05-12

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B11D Dismissal acc. art. 38, par 2 of ipl - failure to pay fee after grant in time