BR112017027806A2 - aprimoramentos orientados por coerência para uma camada de transação de interconexão do componente periférico (pci) expressa (pcie) - Google Patents

aprimoramentos orientados por coerência para uma camada de transação de interconexão do componente periférico (pci) expressa (pcie)

Info

Publication number
BR112017027806A2
BR112017027806A2 BR112017027806A BR112017027806A BR112017027806A2 BR 112017027806 A2 BR112017027806 A2 BR 112017027806A2 BR 112017027806 A BR112017027806 A BR 112017027806A BR 112017027806 A BR112017027806 A BR 112017027806A BR 112017027806 A2 BR112017027806 A2 BR 112017027806A2
Authority
BR
Brazil
Prior art keywords
memory
address range
endpoint
coherence
request
Prior art date
Application number
BR112017027806A
Other languages
English (en)
Inventor
Gil Amit
Lionel Panian James
Rosenberg Ofer
Yohai Yifrach Shaul
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112017027806A2 publication Critical patent/BR112017027806A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

aprimoramentos orientados por coerência para uma camada de transação de pcie são revelados. em um aspecto exemplar, um agente de coerência é adicionado a um sistema de pcie para suportar um modelo de consistência relaxado para uso da memória ali. em particular, os pontos finais podem solicitar a propriedade das porções da memória para ler e gravar na memória. o agente de coerência atribui uma faixa de endereço incluindo as porções solicitadas. o ponto final solicitante copia os conteúdos da memória correspondentes à faixa de endereço atribuída na memória do ponto final local para realizar as operações de leitura e gravação localmente. o ponto final proprietário pode fornecer um instantâneo atualizado dos conteúdos de memória copiados mediante solicitação. ao completar o uso do conteúdo da memória copiada ou mediante solicitação do agente de coerência, a propriedade da faixa de endereços retorna ao complexo raiz e o ponto final envia o conteúdo atualizado de volta para a faixa de endereços no elemento de memória do sistema.
BR112017027806A 2015-06-22 2016-06-17 aprimoramentos orientados por coerência para uma camada de transação de interconexão do componente periférico (pci) expressa (pcie) BR112017027806A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562182815P 2015-06-22 2015-06-22
US15/184,181 US20160371222A1 (en) 2015-06-22 2016-06-16 COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER
PCT/US2016/038146 WO2016209733A1 (en) 2015-06-22 2016-06-17 Coherency driven enhancements to a peripheral component interconnect (pci) express (pcie) transaction layer

Publications (1)

Publication Number Publication Date
BR112017027806A2 true BR112017027806A2 (pt) 2018-08-28

Family

ID=56297124

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017027806A BR112017027806A2 (pt) 2015-06-22 2016-06-17 aprimoramentos orientados por coerência para uma camada de transação de interconexão do componente periférico (pci) expressa (pcie)

Country Status (9)

Country Link
US (1) US20160371222A1 (pt)
EP (1) EP3311279A1 (pt)
JP (1) JP2018518777A (pt)
KR (1) KR20180019595A (pt)
CN (1) CN107980127A (pt)
AU (1) AU2016284002A1 (pt)
BR (1) BR112017027806A2 (pt)
TW (1) TW201701165A (pt)
WO (1) WO2016209733A1 (pt)

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US11301144B2 (en) * 2016-12-28 2022-04-12 Amazon Technologies, Inc. Data storage system
US10514847B2 (en) 2016-12-28 2019-12-24 Amazon Technologies, Inc. Data storage system with multiple durability levels
US10484015B2 (en) 2016-12-28 2019-11-19 Amazon Technologies, Inc. Data storage system with enforced fencing
US10771550B2 (en) 2016-12-28 2020-09-08 Amazon Technologies, Inc. Data storage system with redundant internal networks
US10474620B2 (en) 2017-01-03 2019-11-12 Dell Products, L.P. System and method for improving peripheral component interface express bus performance in an information handling system
JP6704127B2 (ja) * 2017-04-07 2020-06-03 パナソニックＩｐマネジメント株式会社 情報処理装置
US10366027B2 (en) * 2017-11-29 2019-07-30 Advanced Micro Devices, Inc. I/O writes with cache steering
US11169723B2 (en) 2019-06-28 2021-11-09 Amazon Technologies, Inc. Data storage system with metadata check-pointing

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JP2675981B2 (ja) * 1993-09-20 1997-11-12 インターナショナル・ビジネス・マシーンズ・コーポレイション スヌープ・プッシュ・オペレーションを回避する方法
US6018792A (en) * 1997-07-02 2000-01-25 Micron Electronics, Inc. Apparatus for performing a low latency memory read with concurrent snoop
US20040128269A1 (en) * 2002-12-27 2004-07-01 Milligan Charles A. System and method for managing data through families of inter-related metadata tables
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US20070233928A1 (en) * 2006-03-31 2007-10-04 Robert Gough Mechanism and apparatus for dynamically providing required resources for a hot-added PCI express endpoint or hierarchy
US7860930B2 (en) * 2006-12-19 2010-12-28 International Business Machines Corporation Communication between host systems using a transaction protocol and shared memories
US7836129B2 (en) * 2006-12-19 2010-11-16 International Business Machines Corporation Communication between host systems using a queuing system and shared memories
US20090006668A1 (en) * 2007-06-28 2009-01-01 Anil Vasudevan Performing direct data transactions with a cache memory
CN101178697B (zh) * 2007-12-12 2011-08-03 杭州华三通信技术有限公司 一种pcie设备通信方法及系统
CN101276318B (zh) * 2008-05-12 2010-06-09 北京航空航天大学 基于pci-e总线的直接存取数据传输控制装置
CN102549555B (zh) * 2009-10-07 2015-04-22 惠普发展公司，有限责任合伙企业 主机存储器的基于通知协议的端点高速缓存
US9002790B2 (en) * 2011-09-14 2015-04-07 Google Inc. Hosted storage locking
US9189441B2 (en) * 2012-10-19 2015-11-17 Intel Corporation Dual casting PCIE inbound writes to memory and peer devices
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Also Published As

Publication number Publication date
CN107980127A (zh) 2018-05-01
KR20180019595A (ko) 2018-02-26
WO2016209733A1 (en) 2016-12-29
AU2016284002A1 (en) 2017-11-23
JP2018518777A (ja) 2018-07-12
TW201701165A (zh) 2017-01-01
EP3311279A1 (en) 2018-04-25
US20160371222A1 (en) 2016-12-22

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements