BR112014022764A8 - Método de atribuição de memória e sistema para controle de atribuição de memória para memória que é acessível em um ambiente de sistema operacional de um processador multicore - Google Patents

Método de atribuição de memória e sistema para controle de atribuição de memória para memória que é acessível em um ambiente de sistema operacional de um processador multicore

Info

Publication number
BR112014022764A8
BR112014022764A8 BR112014022764A BR112014022764A BR112014022764A8 BR 112014022764 A8 BR112014022764 A8 BR 112014022764A8 BR 112014022764 A BR112014022764 A BR 112014022764A BR 112014022764 A BR112014022764 A BR 112014022764A BR 112014022764 A8 BR112014022764 A8 BR 112014022764A8
Authority
BR
Brazil
Prior art keywords
memory
allocation
memory elements
memory allocation
accessible
Prior art date
Application number
BR112014022764A
Other languages
English (en)
Other versions
BR112014022764B1 (pt
BR112014022764A2 (pt
Inventor
Dilip Dixit Amol
Michael Waters Bradley
Original Assignee
Microsoft Corp
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp, Microsoft Technology Licensing Llc filed Critical Microsoft Corp
Publication of BR112014022764A2 publication Critical patent/BR112014022764A2/pt
Publication of BR112014022764A8 publication Critical patent/BR112014022764A8/pt
Publication of BR112014022764B1 publication Critical patent/BR112014022764B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)

Abstract

MÉTODO E SISTEMA PARA GERENCIAR A ATRIBUIÇÃO DE UMA PLURALIDADE DE ELEMENTOS DE MEMÓRIA E MEIO DE ARMAZENAMENTO LEGÍVEL POR COMPUTADOR. A invenção refere-se a sistemas e técnicas de gerenciamento da atribuição de uma pluralidade de elementos de memória armazenados dentro de uma pluralidade de estruturas de lista sem bloqueio que são apresentados. Estas estruturas de lista sem bloqueio (tal como Slists) podem ser acessíveis dentro de um ambiente de sistema operacional de um processador multicore - e podem ser particionadas dentro do sistema. Os elementos de memória também podem ser particionados entre estas estruturas de lista sem bloqueio. Quando um processador core (ou outro elemento de processamento) faz uma solicitação para a atribuição de um elemento de memória para si mesmo, o sistema e/ou método pode pesquisar entre as estruturas de lista sem bloqueio para um elemento de memória disponível. Quando um elemento de memória adequado e/ou disponível for encontrado, o sistema pode alocar o elemento de memória disponível para solicitar o processador core. Dinamicamente, o equilíbrio dos elementos de memória pode ocorrer de acordo com uma métrica de equilíbrio adequado, tal como manter a igualdade numérica substancial dos elementos de memória ou evitar o excesso de atribuição de recursos.
BR112014022764-0A 2012-04-27 2013-04-19 Método de atribuição de memória e sistema para controle de atribuição de memória para memória que é acessível em um ambiente de sistema operacional de um processador multicore BR112014022764B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/458,355 2012-04-27
US13/458,355 US9652289B2 (en) 2012-04-27 2012-04-27 Systems and methods for S-list partitioning
PCT/US2013/037266 WO2013163008A1 (en) 2012-04-27 2013-04-19 Systems and methods for partitioning of singly linked lists for allocation memory elements

Publications (3)

Publication Number Publication Date
BR112014022764A2 BR112014022764A2 (pt) 2017-06-20
BR112014022764A8 true BR112014022764A8 (pt) 2017-12-12
BR112014022764B1 BR112014022764B1 (pt) 2021-10-13

Family

ID=48289638

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014022764-0A BR112014022764B1 (pt) 2012-04-27 2013-04-19 Método de atribuição de memória e sistema para controle de atribuição de memória para memória que é acessível em um ambiente de sistema operacional de um processador multicore

Country Status (8)

Country Link
US (2) US9652289B2 (pt)
EP (1) EP2842032B1 (pt)
JP (1) JP6275119B2 (pt)
CN (1) CN104254839B (pt)
BR (1) BR112014022764B1 (pt)
RU (1) RU2639944C2 (pt)
TW (1) TWI605340B (pt)
WO (1) WO2013163008A1 (pt)

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US9377954B2 (en) * 2014-05-09 2016-06-28 Advanced Micro Devices, Inc. System and method for memory allocation in a multiclass memory system
US9870328B2 (en) * 2014-11-14 2018-01-16 Cavium, Inc. Managing buffered communication between cores
US10564865B2 (en) 2016-03-22 2020-02-18 Seagate Technology Llc Lockless parity management in a distributed data storage system
WO2018032519A1 (zh) * 2016-08-19 2018-02-22 华为技术有限公司 一种资源分配方法、装置及numa系统
CN107944297B (zh) * 2017-12-11 2020-11-24 北京奇虎科技有限公司 一种访问文件的控制方法及装置
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CN111143058A (zh) * 2019-12-17 2020-05-12 长沙新弘软件有限公司 一种基于后备列表的内存管理方法

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Also Published As

Publication number Publication date
EP2842032B1 (en) 2020-05-06
BR112014022764B1 (pt) 2021-10-13
RU2014143063A (ru) 2016-05-20
EP2842032A1 (en) 2015-03-04
US20170249243A1 (en) 2017-08-31
TWI605340B (zh) 2017-11-11
JP2015515076A (ja) 2015-05-21
US20130290667A1 (en) 2013-10-31
BR112014022764A2 (pt) 2017-06-20
US10223253B2 (en) 2019-03-05
CN104254839A (zh) 2014-12-31
US9652289B2 (en) 2017-05-16
CN104254839B (zh) 2018-10-12
RU2639944C2 (ru) 2017-12-25
WO2013163008A1 (en) 2013-10-31
JP6275119B2 (ja) 2018-02-07
TW201405308A (zh) 2014-02-01

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Legal Events

Date Code Title Description
B25A Requested transfer of rights approved

Owner name: MICROSOFT TECHNOLOGY LICENSING, LLC (US)

B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 19/04/2013, OBSERVADAS AS CONDICOES LEGAIS.