BR112016002454A2 - sistema e método para intercalação de canal de memória com energia seletiva ou otimização de desempenho - Google Patents

sistema e método para intercalação de canal de memória com energia seletiva ou otimização de desempenho

Info

Publication number
BR112016002454A2
BR112016002454A2 BR112016002454A BR112016002454A BR112016002454A2 BR 112016002454 A2 BR112016002454 A2 BR 112016002454A2 BR 112016002454 A BR112016002454 A BR 112016002454A BR 112016002454 A BR112016002454 A BR 112016002454A BR 112016002454 A2 BR112016002454 A2 BR 112016002454A2
Authority
BR
Brazil
Prior art keywords
memory
performance
interleaved
channel interleaving
region
Prior art date
Application number
BR112016002454A
Other languages
English (en)
Other versions
BR112016002454B1 (pt
Inventor
Tu Alex
Chun Dexter
Lo Haw-Jing
Li Yanru
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016002454A2 publication Critical patent/BR112016002454A2/pt
Publication of BR112016002454B1 publication Critical patent/BR112016002454B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

sistemas e métodos são descritos para fornecimento de intercalação de canal de memória com energia seletiva ou otimização de desempenho. um método envolve a configuração de um mapa de endereço de memória para dois ou mais dispositivos de memória acessados através de dois ou mais canais de memória respectivos com uma região intercalada e uma região linear. a região intercalada compreende um espaço de endereço intercalado para casos de utilização de desempenho relativamente mais alto. a região linear compreende um espaço de endereço linear para casos de utilização de energia relativamente menor. solicitações de memória são recebidas de um ou mais clientes. as solicitações de memória compreendem uma preferência por economia de energia ou desempenho. as solicitações de memória recebidas são designadas para a região linear ou região intercalada de acordo com a preferência por economia de energia ou desempenho.
BR112016002454-0A 2013-08-08 2014-08-07 Sistema e método para intercalação de canal de memória com energia seletiva ou otimização de desempenho BR112016002454B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/962,746 US9612648B2 (en) 2013-08-08 2013-08-08 System and method for memory channel interleaving with selective power or performance optimization
US13/962,746 2013-08-08
PCT/US2014/050208 WO2015021316A1 (en) 2013-08-08 2014-08-07 System and method for memory channel interleaving with selective power or performance optimization

Publications (2)

Publication Number Publication Date
BR112016002454A2 true BR112016002454A2 (pt) 2017-08-01
BR112016002454B1 BR112016002454B1 (pt) 2022-01-04

Family

ID=51422152

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016002454-0A BR112016002454B1 (pt) 2013-08-08 2014-08-07 Sistema e método para intercalação de canal de memória com energia seletiva ou otimização de desempenho

Country Status (8)

Country Link
US (1) US9612648B2 (pt)
EP (1) EP3030949B1 (pt)
JP (1) JP6178512B2 (pt)
KR (1) KR101753020B1 (pt)
CN (1) CN105452986B (pt)
BR (1) BR112016002454B1 (pt)
CA (1) CA2918091C (pt)
WO (1) WO2015021316A1 (pt)

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US20170108914A1 (en) * 2015-10-16 2017-04-20 Qualcomm Incorporated System and method for memory channel interleaving using a sliding threshold address
US20170109090A1 (en) * 2015-10-16 2017-04-20 Qualcomm Incorporated System and method for page-by-page memory channel interleaving
US20170162235A1 (en) * 2015-12-02 2017-06-08 Qualcomm Incorporated System and method for memory management using dynamic partial channel interleaving
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CN107291537A (zh) * 2017-06-07 2017-10-24 江苏海平面数据科技有限公司 一种gpu片上存储空间使用的优化方法
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CN112513824B (zh) * 2018-07-31 2024-04-09 华为技术有限公司 一种内存交织方法及装置
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Also Published As

Publication number Publication date
JP2016529618A (ja) 2016-09-23
KR20160040289A (ko) 2016-04-12
CN105452986B (zh) 2018-06-12
BR112016002454B1 (pt) 2022-01-04
EP3030949B1 (en) 2019-05-22
US20150046732A1 (en) 2015-02-12
KR101753020B1 (ko) 2017-07-03
WO2015021316A1 (en) 2015-02-12
CA2918091C (en) 2021-03-02
CA2918091A1 (en) 2015-02-12
US9612648B2 (en) 2017-04-04
JP6178512B2 (ja) 2017-08-09
CN105452986A (zh) 2016-03-30
EP3030949A1 (en) 2016-06-15

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 07/08/2014, OBSERVADAS AS CONDICOES LEGAIS.