BR112015021438A2 - ordenamento de preenchimentos de memóra cache com primeira palavra crítica para acelerar acessos a memória cache e sistemas e métodos baseados em processador conexos - Google Patents

ordenamento de preenchimentos de memóra cache com primeira palavra crítica para acelerar acessos a memória cache e sistemas e métodos baseados em processador conexos

Info

Publication number
BR112015021438A2
BR112015021438A2 BR112015021438A BR112015021438A BR112015021438A2 BR 112015021438 A2 BR112015021438 A2 BR 112015021438A2 BR 112015021438 A BR112015021438 A BR 112015021438A BR 112015021438 A BR112015021438 A BR 112015021438A BR 112015021438 A2 BR112015021438 A2 BR 112015021438A2
Authority
BR
Brazil
Prior art keywords
cache
cache line
word
sorting
series
Prior art date
Application number
BR112015021438A
Other languages
English (en)
Portuguese (pt)
Inventor
Dong Xiangyu
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112015021438A2 publication Critical patent/BR112015021438A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR112015021438A 2013-03-07 2014-03-04 ordenamento de preenchimentos de memóra cache com primeira palavra crítica para acelerar acessos a memória cache e sistemas e métodos baseados em processador conexos BR112015021438A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361773951P 2013-03-07 2013-03-07
US13/925,874 US20140258636A1 (en) 2013-03-07 2013-06-25 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods
PCT/US2014/020229 WO2014138029A1 (en) 2013-03-07 2014-03-04 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods

Publications (1)

Publication Number Publication Date
BR112015021438A2 true BR112015021438A2 (pt) 2017-07-18

Family

ID=51489354

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015021438A BR112015021438A2 (pt) 2013-03-07 2014-03-04 ordenamento de preenchimentos de memóra cache com primeira palavra crítica para acelerar acessos a memória cache e sistemas e métodos baseados em processador conexos

Country Status (7)

Country Link
US (1) US20140258636A1 (https=)
EP (1) EP2965209A1 (https=)
JP (1) JP6377084B2 (https=)
KR (1) KR20150130354A (https=)
CN (1) CN105027094A (https=)
BR (1) BR112015021438A2 (https=)
WO (1) WO2014138029A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102719242B1 (ko) * 2016-10-24 2024-10-22 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10599585B2 (en) * 2017-03-23 2020-03-24 Intel Corporation Least recently used-based hotness tracking mechanism enhancements for high performance caching
US10380034B2 (en) * 2017-07-14 2019-08-13 International Business Machines Corporation Cache return order optimization
WO2021127833A1 (en) * 2019-12-23 2021-07-01 Micron Technology, Inc. Effective avoidance of line cache misses
KR200492757Y1 (ko) 2020-04-13 2020-12-04 주식회사 케이티 서비스 북부 Tv 셋탑박스 걸이구

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781923A (en) * 1996-05-28 1998-07-14 Hewlett-Packard Company Adding a field to the cache tag in a computer system to indicate byte ordering
US6360297B1 (en) * 1999-11-09 2002-03-19 International Business Machines Corporation System bus read address operations with data ordering preference hint bits for vertical caches
US20040103251A1 (en) * 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
US7162583B2 (en) * 2003-12-29 2007-01-09 Intel Corporation Mechanism to store reordered data with compression
US7293141B1 (en) * 2005-02-01 2007-11-06 Advanced Micro Devices, Inc. Cache word of interest latency organization
US8205262B2 (en) * 2006-05-16 2012-06-19 Bird Peter L Hardware support for computer speciation
US8271729B2 (en) * 2009-09-18 2012-09-18 International Business Machines Corporation Read and write aware cache storing cache lines in a read-often portion and a write-often portion

Also Published As

Publication number Publication date
US20140258636A1 (en) 2014-09-11
JP6377084B2 (ja) 2018-08-22
JP2016509324A (ja) 2016-03-24
KR20150130354A (ko) 2015-11-23
EP2965209A1 (en) 2016-01-13
CN105027094A (zh) 2015-11-04
WO2014138029A1 (en) 2014-09-12

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]