BR112012027002A2 - dispositivo de aplicação de tensões em um circuito integrado e processo de aplicação de tensões em circuito integrado - Google Patents

dispositivo de aplicação de tensões em um circuito integrado e processo de aplicação de tensões em circuito integrado

Info

Publication number
BR112012027002A2
BR112012027002A2 BR112012027002A BR112012027002A BR112012027002A2 BR 112012027002 A2 BR112012027002 A2 BR 112012027002A2 BR 112012027002 A BR112012027002 A BR 112012027002A BR 112012027002 A BR112012027002 A BR 112012027002A BR 112012027002 A2 BR112012027002 A2 BR 112012027002A2
Authority
BR
Brazil
Prior art keywords
integrated circuit
circuit voltage
voltage applying
applying device
applying process
Prior art date
Application number
BR112012027002A
Other languages
English (en)
Inventor
Alexandre Douin
Christian Binois
Daniel Peyre
Florian Moliere
Gerard Salvaterra
Sébastien Morand
Original Assignee
Eads Europ Aeronautic Defence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eads Europ Aeronautic Defence filed Critical Eads Europ Aeronautic Defence
Publication of BR112012027002A2 publication Critical patent/BR112012027002A2/pt

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2898—Sample preparation, e.g. removing encapsulation, etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Electromagnetism (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Lasers (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
BR112012027002A 2010-04-20 2011-04-19 dispositivo de aplicação de tensões em um circuito integrado e processo de aplicação de tensões em circuito integrado BR112012027002A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1052978A FR2959018B1 (fr) 2010-04-20 2010-04-20 Procedes et dispositifs de mise sous contrainte d'un circuit integre
PCT/EP2011/056235 WO2011131669A1 (fr) 2010-04-20 2011-04-19 Procédés et dispositifs de mise sous contrainte d'un circuit intégré

Publications (1)

Publication Number Publication Date
BR112012027002A2 true BR112012027002A2 (pt) 2016-07-19

Family

ID=43384634

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112012027002A BR112012027002A2 (pt) 2010-04-20 2011-04-19 dispositivo de aplicação de tensões em um circuito integrado e processo de aplicação de tensões em circuito integrado

Country Status (9)

Country Link
US (1) US9618567B2 (pt)
EP (2) EP2910960A1 (pt)
CN (1) CN103038654B (pt)
BR (1) BR112012027002A2 (pt)
CA (1) CA2797015A1 (pt)
ES (1) ES2545008T3 (pt)
FR (1) FR2959018B1 (pt)
IL (1) IL222523A0 (pt)
WO (1) WO2011131669A1 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3004262B1 (fr) * 2013-04-09 2015-05-15 Eads Europ Aeronautic Defence Procede d'etude de la fiabilite en temperature d'un composant electronique
CN110927561B (zh) * 2019-12-19 2021-08-24 江西智慧云测安全检测中心股份有限公司 一种单点激光测试平台

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3774078A (en) * 1972-03-29 1973-11-20 Massachusetts Inst Technology Thermally integrated electronic assembly with tapered heat conductor
DE3263256D1 (en) * 1981-07-08 1985-05-30 Fujitsu Ltd Device for testing semiconductor devices at a high temperature
US4639829A (en) * 1984-06-29 1987-01-27 International Business Machines Corporation Thermal conduction disc-chip cooling enhancement means
JPS6293965A (ja) * 1985-10-21 1987-04-30 Hitachi Ltd 集積回路冷却構造
US5045914A (en) * 1989-12-26 1991-09-03 Motorola, Inc. Plastic pad array electronic AC device
US5164661A (en) * 1991-05-31 1992-11-17 Ej Systems, Inc. Thermal control system for a semi-conductor burn-in
US5895972A (en) * 1996-12-31 1999-04-20 Intel Corporation Method and apparatus for cooling the backside of a semiconductor device using an infrared transparent heat slug
US5848122A (en) * 1997-03-25 1998-12-08 Advanced Technology Materials, Inc. Apparatus for rapid in-situ X-ray stress measurement during thermal cycling of semiconductor wafers
US6570247B1 (en) * 1997-12-30 2003-05-27 Intel Corporation Integrated circuit device having an embedded heat slug
US6483326B1 (en) * 1999-08-10 2002-11-19 Advanced Micro Devices, Inc. Localized heating for defect isolation during die operation
US6476597B1 (en) * 2000-01-18 2002-11-05 Full Circle Research, Inc. Ionizing dose hardness assurance technique for CMOS integrated circuits
JP3813512B2 (ja) * 2002-01-07 2006-08-23 株式会社東芝 貼り合わせ基板の評価方法及び評価装置、半導体装置の製造方法
US6836014B2 (en) * 2002-10-03 2004-12-28 Credence Systems Corporation Optical testing of integrated circuits with temperature control
US7259580B2 (en) * 2005-02-22 2007-08-21 International Business Machines Corporation Method and apparatus for temporary thermal coupling of an electronic device to a heat sink during test
JP3767829B1 (ja) * 2005-06-09 2006-04-19 エスティケイテクノロジー株式会社 半導体デバイスの検査装置
CN101398457B (zh) * 2007-09-25 2011-06-15 奇景光电股份有限公司 晶片、其测试系统、其测试方法及其测试治具
US7777514B2 (en) * 2008-01-04 2010-08-17 Texas Instruments Incorporated Methods for transferring integrated circuits to a printed circuit board
CN101252099B (zh) * 2008-03-18 2012-03-28 日月光半导体制造股份有限公司 温度循环测试装置及利用此装置加热芯片倒装封装结构
WO2010056769A2 (en) * 2008-11-14 2010-05-20 Applied Materials, Inc. Eddy current sensor with enhanced edge resolution
US8248097B2 (en) * 2009-04-02 2012-08-21 International Business Machines Corporation Method and apparatus for probing a wafer
TW201201957A (en) * 2010-01-29 2012-01-16 Applied Materials Inc High sensitivity real time profile control eddy current monitoring system

Also Published As

Publication number Publication date
IL222523A0 (en) 2012-12-31
CN103038654B (zh) 2015-11-25
ES2545008T3 (es) 2015-09-07
EP2561373B1 (fr) 2015-06-03
US9618567B2 (en) 2017-04-11
FR2959018B1 (fr) 2012-08-31
US20130193995A1 (en) 2013-08-01
FR2959018A1 (fr) 2011-10-21
CN103038654A (zh) 2013-04-10
WO2011131669A1 (fr) 2011-10-27
EP2910960A1 (fr) 2015-08-26
CA2797015A1 (fr) 2011-10-27
EP2561373A1 (fr) 2013-02-27

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06T Formal requirements before examination [chapter 6.20 patent gazette]
B11E Dismissal acc. art. 34 of ipl - requirements for examination incomplete
B11T Dismissal of application maintained [chapter 11.20 patent gazette]