BR0102189A - Circuito programável com função de visualizaçãoprévia - Google Patents

Circuito programável com função de visualizaçãoprévia

Info

Publication number
BR0102189A
BR0102189A BR0102189-3A BR0102189A BR0102189A BR 0102189 A BR0102189 A BR 0102189A BR 0102189 A BR0102189 A BR 0102189A BR 0102189 A BR0102189 A BR 0102189A
Authority
BR
Brazil
Prior art keywords
input structure
programmable circuit
circuit
common node
signal
Prior art date
Application number
BR0102189-3A
Other languages
English (en)
Inventor
Christopher R Morton
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of BR0102189A publication Critical patent/BR0102189A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Abstract

Patente de Invenção: "CIRCUITO PROGRAMáVEL COMFUNçãO DE VISUALIZAçãO PRéVIA". A presente invençãorefere-se a um circuito programável que pode ser conectado comuma primeira fonte de voltagem para proporcionar uma voltagempredeterminada, esse circuito compreendendo: uma primeiraestrutura de entrada conectada com um nó comum, onde umprimeiro sinal é colocado na estrutura de entrada de teste e oestado do circuito programável é temporariamente estabelecido;um transistor que pode ser conectado com uma segunda fonte devoltagem proporcionando uma segunda voltagem predeterminadae com o nó comum; um resistor que pode ser conectado entre aprimeira fonte de voltagem e o nó comum; e uma segunda estruturade entrada conectada com o transistor, onde um sinal de ativaçãode programação é aplicado junto a segunda estrutura de entrada,para que um sinal de programação possa ser aplicado junto aprimeira estrutura de entrada para permanentemente estabelecer ocircuito.
BR0102189-3A 2000-05-01 2001-04-30 Circuito programável com função de visualizaçãoprévia BR0102189A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/562,099 US6307423B1 (en) 2000-05-01 2000-05-01 Programmable circuit with preview function

Publications (1)

Publication Number Publication Date
BR0102189A true BR0102189A (pt) 2001-12-26

Family

ID=24244784

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0102189-3A BR0102189A (pt) 2000-05-01 2001-04-30 Circuito programável com função de visualizaçãoprévia

Country Status (6)

Country Link
US (2) US6307423B1 (pt)
EP (1) EP1154438B1 (pt)
JP (1) JP4398108B2 (pt)
BR (1) BR0102189A (pt)
CA (1) CA2345570C (pt)
DE (1) DE60118458T2 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187228B1 (en) * 2001-06-22 2007-03-06 Quicklogic Corporation Method of programming an antifuse
US6549063B1 (en) * 2002-01-11 2003-04-15 Infineon Technologies Ag Evaluation circuit for an anti-fuse
EP1573747B1 (en) * 2002-12-12 2009-10-21 Nxp B.V. One-time programmable memory device
WO2009044237A1 (en) * 2007-10-03 2009-04-09 Stmicroelectronics Crolles 2 Sas Anti-fuse element
CN103414459B (zh) * 2013-09-05 2016-04-13 青岛歌尔声学科技有限公司 带禁能/使能功能的模拟信号输入控制电路
CN103700405B (zh) * 2013-12-04 2016-06-15 无锡华润矽科微电子有限公司 可模拟熔断的熔丝电路
US20230318588A1 (en) * 2022-03-31 2023-10-05 Texas Instruments Incorporated Signal chatter mitigation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231156A (ja) * 1985-08-02 1987-02-10 Nec Corp 半導体装置及びその製造方法
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5382843A (en) * 1990-02-02 1995-01-17 Gucyski; Jeff One or two transistor logic with temperature compensation and minimized supply voltage
JPH07260874A (ja) * 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置及びその試験方法
JP3714696B2 (ja) * 1994-10-21 2005-11-09 富士通株式会社 半導体記憶装置
US6037798A (en) * 1996-05-08 2000-03-14 Telefonaktiebolaget Lm Ericsson Line receiver circuit having termination impedances with transmission gates connected in parallel
JP3274364B2 (ja) * 1996-08-14 2002-04-15 株式会社東芝 半導体装置及びヒューズチェック方法
JPH11232869A (ja) * 1998-02-16 1999-08-27 Mitsubishi Electric Corp 半導体回路装置
US6037831A (en) * 1998-03-30 2000-03-14 Xerox Corporation Fusible link circuit including a preview feature
US6031275A (en) * 1998-12-15 2000-02-29 National Semiconductor Corporation Antifuse with a silicide layer overlying a diffusion region
US6222389B1 (en) * 1999-03-25 2001-04-24 International Business Machines Corporation Assisted gunning transceiver logic (AGTL) bus driver

Also Published As

Publication number Publication date
CA2345570C (en) 2003-12-30
DE60118458D1 (de) 2006-05-18
US20020000832A1 (en) 2002-01-03
CA2345570A1 (en) 2001-11-01
US6392436B2 (en) 2002-05-21
DE60118458T2 (de) 2006-08-24
EP1154438A3 (en) 2003-10-29
JP4398108B2 (ja) 2010-01-13
JP2002076130A (ja) 2002-03-15
EP1154438B1 (en) 2006-04-05
US6307423B1 (en) 2001-10-23
EP1154438A2 (en) 2001-11-14

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ARTIGO 8O COMBINADO COM ARTIGO 13 DA LPI.

B09B Patent application refused [chapter 9.2 patent gazette]

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