BR0015304A - Método e aparelho para suportar propagação de multirelógio em um sistema de computador tendo uma interconexão semidúplex de ponto a ponto - Google Patents

Método e aparelho para suportar propagação de multirelógio em um sistema de computador tendo uma interconexão semidúplex de ponto a ponto

Info

Publication number
BR0015304A
BR0015304A BR0015304-4A BR0015304A BR0015304A BR 0015304 A BR0015304 A BR 0015304A BR 0015304 A BR0015304 A BR 0015304A BR 0015304 A BR0015304 A BR 0015304A
Authority
BR
Brazil
Prior art keywords
point
mch
computer system
ich
request
Prior art date
Application number
BR0015304-4A
Other languages
English (en)
Inventor
David J Harriman
Randy B Osborne
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR0015304A publication Critical patent/BR0015304A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

Patente de Invenção: "MéTODO E APARELHO PARA SUPORTAR PROPAGAçãO DE MULTIRELóGIO EM UM SISTEMA DE COMPUTADOR TENDO UMA INTERCONEXãO SEMIDúPLEX DE PONTO A PONTO". De acordo com uma modalidade, um sistema de computador compreende uma unidade de processamento central (CPU), um centro de conexão de controle de memória (MCH) acoplado na CPU, uma interface de ponto a ponto acoplada no MCH e um centro de conexão de controle de entrada/saída (ICH) acoplado na interface de ponto a ponto. O MCH retarda a arbitragem de uma solicitação para acessar a interface de ponto a ponto até que a solicitação de acesso é recebida no ICH e o ICH retarda a arbitragem de uma solicitação para acessar a interface de ponto a ponto até que a solicitação de acesso é recebida no MCH.
BR0015304-4A 1999-11-03 2000-09-29 Método e aparelho para suportar propagação de multirelógio em um sistema de computador tendo uma interconexão semidúplex de ponto a ponto BR0015304A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/433,653 US6347351B1 (en) 1999-11-03 1999-11-03 Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect
PCT/US2000/026875 WO2001033375A1 (en) 1999-11-03 2000-09-29 Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect

Publications (1)

Publication Number Publication Date
BR0015304A true BR0015304A (pt) 2002-07-09

Family

ID=23721016

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0015304-4A BR0015304A (pt) 1999-11-03 2000-09-29 Método e aparelho para suportar propagação de multirelógio em um sistema de computador tendo uma interconexão semidúplex de ponto a ponto

Country Status (9)

Country Link
US (1) US6347351B1 (pt)
EP (1) EP1226504B1 (pt)
CN (1) CN1205560C (pt)
AU (1) AU7737700A (pt)
BR (1) BR0015304A (pt)
DE (1) DE60017774T2 (pt)
HK (1) HK1044610A1 (pt)
TW (1) TW486630B (pt)
WO (1) WO2001033375A1 (pt)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107371B1 (en) 1997-09-22 2006-09-12 Intel Corporation Method and apparatus for providing and embedding control information in a bus system
US6088370A (en) * 1997-09-22 2000-07-11 Intel Corporation Fast 16 bit, split transaction I/O bus
US6748442B1 (en) * 1998-12-21 2004-06-08 Advanced Micro Devices, Inc. Method and apparatus for using a control signal on a packet based communication link
US6615306B1 (en) * 1999-11-03 2003-09-02 Intel Corporation Method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface
US7039047B1 (en) 1999-11-03 2006-05-02 Intel Corporation Virtual wire signaling
TW468112B (en) * 1999-12-15 2001-12-11 Via Tech Inc Arbitrating method of bus between control chipsets
US6877052B1 (en) 2000-09-29 2005-04-05 Intel Corporation System and method for improved half-duplex bus performance
US7000691B1 (en) * 2002-07-11 2006-02-21 Raytheon Company Method and apparatus for cooling with coolant at a subambient pressure
US8356124B1 (en) * 2004-05-14 2013-01-15 Emc Corporation Method and system for processing packet transfers
DE102004031715B4 (de) * 2004-06-30 2013-05-29 Globalfoundries Inc. Kombinierte On-Chip-Befehls- und Antwortdatenschnittstelle
CN100362504C (zh) * 2005-01-21 2008-01-16 瑞传科技股份有限公司 用于工业电脑的单板电脑机板
JP4455540B2 (ja) * 2006-06-15 2010-04-21 キヤノン株式会社 バスシステム及び調停方法
JP4600509B2 (ja) * 2008-04-22 2010-12-15 セイコーエプソン株式会社 送受信システム並びにマスターデバイス
JP5418193B2 (ja) * 2009-12-14 2014-02-19 富士ゼロックス株式会社 調停装置、画像処理装置、及び画像形成システム
US8667197B2 (en) * 2010-09-08 2014-03-04 Intel Corporation Providing a fine-grained arbitration system
FR3093197A1 (fr) * 2019-02-21 2020-08-28 Stmicroelectronics (Grenoble 2) Sas Procédé d’arbitrage d’accès à une mémoire partagée, et dispositif électronique correspondant

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0552507B1 (en) 1991-12-04 1998-02-11 Koninklijke Philips Electronics N.V. Arbiter with a direct signal that is modifiable under priority-conflict control
DE4426123C2 (de) 1994-07-22 1998-05-20 Siemens Nixdorf Inf Syst Arbitrierung bei verzögernder Buskopplung
US5682508A (en) 1995-03-23 1997-10-28 Onset Computer Corporation UART protocol that provides predictable delay for communication between computers of disparate ability
US6145039A (en) * 1998-11-03 2000-11-07 Intel Corporation Method and apparatus for an improved interface between computer components
US6256697B1 (en) * 1998-12-30 2001-07-03 Intel Corporation Method and apparatus for reusing arbitration signals to frame data transfers between hub agents

Also Published As

Publication number Publication date
EP1226504A1 (en) 2002-07-31
HK1044610A1 (en) 2002-10-25
CN1423779A (zh) 2003-06-11
US6347351B1 (en) 2002-02-12
CN1205560C (zh) 2005-06-08
WO2001033375A1 (en) 2001-05-10
EP1226504B1 (en) 2005-01-26
AU7737700A (en) 2001-05-14
DE60017774D1 (de) 2005-03-03
DE60017774T2 (de) 2006-01-05
TW486630B (en) 2002-05-11

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ARTIGO 8O COMBINADO COM 13 DA LPI

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.