BG45675A1 - Controlling device for direct access - Google Patents

Controlling device for direct access

Info

Publication number
BG45675A1
BG45675A1 BG8145587A BG8145587A BG45675A1 BG 45675 A1 BG45675 A1 BG 45675A1 BG 8145587 A BG8145587 A BG 8145587A BG 8145587 A BG8145587 A BG 8145587A BG 45675 A1 BG45675 A1 BG 45675A1
Authority
BG
Bulgaria
Prior art keywords
controlling device
direct access
access
direct
controlling
Prior art date
Application number
BG8145587A
Other languages
English (en)
Inventor
Venelin G Barbutov
Khristo A Turlakov
Dimitar D Rachev
Original Assignee
Tsentralen Inst Za Izchislitel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsentralen Inst Za Izchislitel filed Critical Tsentralen Inst Za Izchislitel
Priority to BG8145587A priority Critical patent/BG45675A1/xx
Priority to HU527388A priority patent/HUT48761A/hu
Priority to DE19883835125 priority patent/DE3835125A1/de
Priority to GB8824093A priority patent/GB2211325A/en
Priority to JP26129988A priority patent/JPH01236342A/ja
Publication of BG45675A1 publication Critical patent/BG45675A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
BG8145587A 1987-10-16 1987-10-16 Controlling device for direct access BG45675A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BG8145587A BG45675A1 (en) 1987-10-16 1987-10-16 Controlling device for direct access
HU527388A HUT48761A (en) 1987-10-16 1988-10-12 8-bit control device of direct memory access (dma)
DE19883835125 DE3835125A1 (de) 1987-10-16 1988-10-14 8-bit-steuereinrichtung fuer direkten zugriff
GB8824093A GB2211325A (en) 1987-10-16 1988-10-14 DMA controller
JP26129988A JPH01236342A (ja) 1987-10-16 1988-10-17 Ｄｍａコントローラ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG8145587A BG45675A1 (en) 1987-10-16 1987-10-16 Controlling device for direct access

Publications (1)

Publication Number Publication Date
BG45675A1 true BG45675A1 (en) 1989-07-14

Family

ID=3919643

Family Applications (1)

Application Number Title Priority Date Filing Date
BG8145587A BG45675A1 (en) 1987-10-16 1987-10-16 Controlling device for direct access

Country Status (5)

Country Link
JP (1) JPH01236342A (xx)
BG (1) BG45675A1 (xx)
DE (1) DE3835125A1 (xx)
GB (1) GB2211325A (xx)
HU (1) HUT48761A (xx)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381538A (en) * 1991-10-15 1995-01-10 International Business Machines Corp. DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
WO1993023810A1 (en) * 1992-05-12 1993-11-25 Seiko Epson Corporation Scalable coprocessor
US5465332A (en) * 1992-09-21 1995-11-07 International Business Machines Corporation Selectable 8/16 bit DMA channels for "ISA" bus
US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing
JP3519205B2 (ja) * 1996-03-21 2004-04-12 シャープ株式会社 Ｄｍａコントローラ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892025A (ja) * 1981-11-26 1983-06-01 Hitachi Ltd デ−タ処理方式
US4530053A (en) * 1983-04-14 1985-07-16 International Business Machines Corporation DMA multimode transfer controls

Also Published As

Publication number Publication date
JPH01236342A (ja) 1989-09-21
HUT48761A (en) 1989-06-28
GB2211325A (en) 1989-06-28
DE3835125A1 (de) 1989-05-03
GB8824093D0 (en) 1988-11-23

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