BE902811A - Arrangement de circuit pour commander des transferts de donnees bidirectionnels entre un processeur et des lignes de transmission connectees par des unites entree/sortie - Google Patents

Arrangement de circuit pour commander des transferts de donnees bidirectionnels entre un processeur et des lignes de transmission connectees par des unites entree/sortie

Info

Publication number
BE902811A
BE902811A BE2/60738A BE2060738A BE902811A BE 902811 A BE902811 A BE 902811A BE 2/60738 A BE2/60738 A BE 2/60738A BE 2060738 A BE2060738 A BE 2060738A BE 902811 A BE902811 A BE 902811A
Authority
BE
Belgium
Prior art keywords
transmission lines
input
output units
processor
controlling
Prior art date
Application number
BE2/60738A
Other languages
English (en)
Inventor
F Gasser
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Publication of BE902811A publication Critical patent/BE902811A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Logic Circuits (AREA)
  • Image Processing (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

Pour chaque sens de transfert, un tampon (ZP1, ZP2), est fourni. Les deux tampons sont connectés à un processeur (RE) par un bus d'adresse/données (ADB) et à des lignes de transmission respectivement via une unité d'entrée (EE) et une unité de sortie (AE). Une unité logique à seuil programmable (SL1, SL2) est associée avec chacun des tampons (ZP1, ZP2) et elle est connectée au processeur (RE) par le bus d'adresse/données (ABD) et via des moyens logiques de demande d'interruption (IRL).
BE2/60738A 1984-07-04 1985-07-04 Arrangement de circuit pour commander des transferts de donnees bidirectionnels entre un processeur et des lignes de transmission connectees par des unites entree/sortie BE902811A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843424587 DE3424587A1 (de) 1984-07-04 1984-07-04 Schaltungsanordnung zur steuerung der bidirektionalen datenuebertragung zwischen einer rechnereinheit und ueber ein-/ausgabeeinheiten angeschlossenen uebertragungsleitungen

Publications (1)

Publication Number Publication Date
BE902811A true BE902811A (fr) 1986-01-06

Family

ID=6239816

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/60738A BE902811A (fr) 1984-07-04 1985-07-04 Arrangement de circuit pour commander des transferts de donnees bidirectionnels entre un processeur et des lignes de transmission connectees par des unites entree/sortie

Country Status (5)

Country Link
EP (1) EP0170876B1 (fr)
AT (1) ATE69320T1 (fr)
BE (1) BE902811A (fr)
DE (2) DE3424587A1 (fr)
ES (1) ES8704016A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2203616B (en) * 1987-04-01 1991-10-02 Digital Equipment Int Improvements in or relating to data communication systems
DE3727072A1 (de) * 1987-08-14 1989-02-23 Bernd Ihlow Zusatzeinrichtung fuer anlagen mit datenerfassung sowie -ausgabe
US5299315A (en) * 1992-09-17 1994-03-29 International Business Machines Corp. Personal computer with programmable threshold FIFO registers for data transfer
DE4336353C2 (de) * 1992-12-02 1999-04-22 Siemens Ag Mikroprozessor mit einer integrierten Bussteuereinheit
DE4417286A1 (de) * 1994-05-13 1995-11-23 Deutsche Bundespost Telekom Verfahren und Schaltungsanordnung zum Auslesen von Daten aus Pufferspeichern in ATM-Einrichtungen
DE10017362B4 (de) * 2000-04-07 2004-02-12 Infineon Technologies Ag Einrichtung und Verfahren zur Datenübergabe zwischen zwei Recheneinheiten

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
FR2440058A1 (fr) * 1978-10-27 1980-05-23 Materiel Telephonique Systeme de memoire tampon pour unite d'echange entre deux unites fonctionnelles et procede de mise en oeuvre
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system

Also Published As

Publication number Publication date
DE3584592D1 (de) 1991-12-12
ATE69320T1 (de) 1991-11-15
EP0170876A2 (fr) 1986-02-12
ES8704016A1 (es) 1987-02-01
DE3424587A1 (de) 1986-01-09
ES544856A0 (es) 1987-02-01
EP0170876A3 (en) 1988-08-10
EP0170876B1 (fr) 1991-11-06

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Legal Events

Date Code Title Description
CA Change of address of the owner of the patent

Owner name: *ALCATEL N.V.STRAWINSKYLAAN 537, NL-1077 XX AMSTER

Effective date: 19850704

CH Change of patent owner

Owner name: *ALCATEL N.V.

Effective date: 19850704

RE Patent lapsed

Owner name: ALCATEL N.V.

Effective date: 19950731