BE848991A - Procede de realisation de dispositif a semi-conducteur ayant des regions dopees separees par une faible distance reglee avec precision - Google Patents
Procede de realisation de dispositif a semi-conducteur ayant des regions dopees separees par une faible distance reglee avec precisionInfo
- Publication number
- BE848991A BE848991A BE172907A BE172907A BE848991A BE 848991 A BE848991 A BE 848991A BE 172907 A BE172907 A BE 172907A BE 172907 A BE172907 A BE 172907A BE 848991 A BE848991 A BE 848991A
- Authority
- BE
- Belgium
- Prior art keywords
- dopeous
- precision
- semiconductor device
- distance set
- regions separated
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/111—Narrow masking
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05637177 US4038107B1 (en) | 1975-12-03 | 1975-12-03 | Method for making transistor structures |
Publications (1)
Publication Number | Publication Date |
---|---|
BE848991A true BE848991A (fr) | 1977-04-01 |
Family
ID=24554884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE172907A BE848991A (fr) | 1975-12-03 | 1976-12-02 | Procede de realisation de dispositif a semi-conducteur ayant des regions dopees separees par une faible distance reglee avec precision |
Country Status (11)
Country | Link |
---|---|
US (1) | US4038107B1 (xx) |
JP (1) | JPS6038877B2 (xx) |
BE (1) | BE848991A (xx) |
CA (1) | CA1063731A (xx) |
DE (1) | DE2654482A1 (xx) |
ES (1) | ES453911A1 (xx) |
FR (1) | FR2334203A1 (xx) |
GB (1) | GB1558349A (xx) |
IT (1) | IT1106505B (xx) |
NL (1) | NL7613440A (xx) |
SE (1) | SE418031B (xx) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2802838A1 (de) * | 1978-01-23 | 1979-08-16 | Siemens Ag | Mis-feldeffekttransistor mit kurzer kanallaenge |
US4485390A (en) * | 1978-03-27 | 1984-11-27 | Ncr Corporation | Narrow channel FET |
US4212683A (en) * | 1978-03-27 | 1980-07-15 | Ncr Corporation | Method for making narrow channel FET |
US4145233A (en) * | 1978-05-26 | 1979-03-20 | Ncr Corporation | Method for making narrow channel FET by masking and ion-implantation |
US4294002A (en) * | 1979-05-21 | 1981-10-13 | International Business Machines Corp. | Making a short-channel FET |
US4280855A (en) * | 1980-01-23 | 1981-07-28 | Ibm Corporation | Method of making a dual DMOS device by ion implantation and diffusion |
US4343082A (en) * | 1980-04-17 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device |
USRE32613E (en) * | 1980-04-17 | 1988-02-23 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device |
US4758528A (en) * | 1980-07-08 | 1988-07-19 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
US4442589A (en) * | 1981-03-05 | 1984-04-17 | International Business Machines Corporation | Method for manufacturing field effect transistors |
US4691435A (en) * | 1981-05-13 | 1987-09-08 | International Business Machines Corporation | Method for making Schottky diode having limited area self-aligned guard ring |
US5118631A (en) * | 1981-07-10 | 1992-06-02 | Loral Fairchild Corporation | Self-aligned antiblooming structure for charge-coupled devices and method of fabrication thereof |
JPS58137262A (ja) * | 1982-02-09 | 1983-08-15 | Seiko Instr & Electronics Ltd | 静電誘導半導体装置の製造方法 |
DE3219888A1 (de) * | 1982-05-27 | 1983-12-01 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Planares halbleiterbauelement und verfahren zur herstellung |
BE897139A (nl) * | 1983-06-27 | 1983-12-27 | Bell Telephone Mfg Cy Nov | Proces voor het maken van een halfgeleider-inrichting en inrichting hierdoor verkregen |
GB2148589B (en) * | 1983-10-18 | 1987-04-23 | Standard Telephones Cables Ltd | Improvements in intergrated circuits |
GB2199694A (en) * | 1986-12-23 | 1988-07-13 | Philips Electronic Associated | A method of manufacturing a semiconductor device |
US4764482A (en) * | 1986-11-21 | 1988-08-16 | General Electric Company | Method of fabricating an integrated circuit containing bipolar and MOS transistors |
US4923824A (en) * | 1988-04-27 | 1990-05-08 | Vtc Incorporated | Simplified method of fabricating lightly doped drain insulated gate field effect transistors |
US5543646A (en) * | 1988-09-08 | 1996-08-06 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with a shaped gate electrode |
US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
TW203148B (xx) * | 1991-03-27 | 1993-04-01 | American Telephone & Telegraph | |
US5242841A (en) * | 1992-03-25 | 1993-09-07 | Texas Instruments Incorporated | Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate |
US5702967A (en) * | 1996-07-22 | 1997-12-30 | Vanguard International Semiconductor Corporation | Method of fabricating a deep submicron MOSFET device using a recessed, narrow polysilicon gate structure |
JP2001352079A (ja) * | 2000-06-07 | 2001-12-21 | Nec Corp | ダイオードおよびその製造方法 |
KR101024638B1 (ko) * | 2008-08-05 | 2011-03-25 | 매그나칩 반도체 유한회사 | 반도체 소자의 제조방법 |
US8202791B2 (en) * | 2009-03-16 | 2012-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for generating two dimensions for different implant energies |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1053046A (xx) * | 1963-02-25 | 1900-01-01 | ||
US3456168A (en) * | 1965-02-19 | 1969-07-15 | United Aircraft Corp | Structure and method for production of narrow doped region semiconductor devices |
US3406049A (en) * | 1965-04-28 | 1968-10-15 | Ibm | Epitaxial semiconductor layer as a diffusion mask |
US3558366A (en) * | 1968-09-17 | 1971-01-26 | Bell Telephone Labor Inc | Metal shielding for ion implanted semiconductor device |
US3764396A (en) * | 1969-09-18 | 1973-10-09 | Kogyo Gijutsuin | Transistors and production thereof |
US3681147A (en) * | 1970-01-22 | 1972-08-01 | Ibm | Method for masking semiconductor regions for ion implantation |
US3719535A (en) * | 1970-12-21 | 1973-03-06 | Motorola Inc | Hyperfine geometry devices and method for their fabrication |
US3765961A (en) * | 1971-02-12 | 1973-10-16 | Bell Telephone Labor Inc | Special masking method of fabricating a planar avalanche transistor |
US3947299A (en) * | 1971-05-22 | 1976-03-30 | U.S. Philips Corporation | Method of manufacturing semiconductor devices |
US3846822A (en) * | 1973-10-05 | 1974-11-05 | Bell Telephone Labor Inc | Methods for making field effect transistors |
-
1975
- 1975-12-03 US US05637177 patent/US4038107B1/en not_active Expired - Lifetime
-
1976
- 1976-11-17 CA CA265,883A patent/CA1063731A/en not_active Expired
- 1976-11-22 SE SE7613031A patent/SE418031B/xx not_active IP Right Cessation
- 1976-12-01 DE DE19762654482 patent/DE2654482A1/de active Granted
- 1976-12-01 GB GB50058/76A patent/GB1558349A/en not_active Expired
- 1976-12-02 IT IT69889/76A patent/IT1106505B/it active
- 1976-12-02 FR FR7636332A patent/FR2334203A1/fr active Granted
- 1976-12-02 BE BE172907A patent/BE848991A/xx not_active IP Right Cessation
- 1976-12-02 NL NL7613440A patent/NL7613440A/xx not_active Application Discontinuation
- 1976-12-03 JP JP51144854A patent/JPS6038877B2/ja not_active Expired
- 1976-12-03 ES ES453911A patent/ES453911A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5279668A (en) | 1977-07-04 |
IT1106505B (it) | 1985-11-11 |
NL7613440A (nl) | 1977-06-07 |
FR2334203B1 (xx) | 1980-03-14 |
DE2654482C2 (xx) | 1989-04-20 |
ES453911A1 (es) | 1977-11-16 |
SE7613031L (sv) | 1977-06-04 |
GB1558349A (en) | 1979-12-28 |
US4038107A (en) | 1977-07-26 |
US4038107B1 (en) | 1995-04-18 |
SE418031B (sv) | 1981-04-27 |
JPS6038877B2 (ja) | 1985-09-03 |
FR2334203A1 (fr) | 1977-07-01 |
CA1063731A (en) | 1979-10-02 |
DE2654482A1 (de) | 1977-06-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RE20 | Patent expired |
Owner name: WESTERN ELECTRIC CY INC. Effective date: 19961202 |